公开(公告)号：US20160351681A1

公开(公告)日：2016-12-01

申请号：US14727458

申请日：2015-06-01

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Murat Kerem Akarvardar ,  Jody A. Fronheiser ,  Bruce Doris

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L29/7846 ,  H01L29/7848

Abstract: One method disclosed herein includes, among other things, forming a patterned fin having a thickness that is equal to or greater than a target final fin height for a replacement fin, performing an etching process through the patterned fin etch mask to form a plurality of trenches in a semiconductor substrate to define a substrate fin and forming a recessed layer of insulating material in the trenches so as to expose the patterned fin etch. The method also includes forming a layer of CTE-matching material around the exposed patterned fin etch mask, removing the patterned fin etch mask to thereby define a replacement fin cavity and expose a surface of the substrate fin, forming the replacement fin on the substrate fin and in the replacement fin cavity, removing the layer of CTE-matching material and forming a gate structure around at least a portion of the replacement fin.

Abstract translation: 本文公开的一种方法包括形成具有等于或大于用于替换翅片的目标最终翅片高度的厚度的图案化翅片，通过图案化翅片蚀刻掩模执行蚀刻工艺以形成多个沟槽 在半导体衬底中限定衬底鳍并在沟槽中形成绝缘材料的凹陷层，以暴露图案化鳍片蚀刻。 该方法还包括在暴露的图案化鳍状物蚀刻掩模周围形成CTE匹配材料层，去除图案化的鳍状蚀刻掩模，从而限定替换的翅片腔并暴露衬底鳍片的表面，在衬底鳍片上形成置换鳍片 并且在替换翅片腔中，去除CTE匹配材料层并在替换翅片的至少一部分周围形成栅极结构。

公开(公告)号：US09425315B2

公开(公告)日：2016-08-23

申请号：US14811921

申请日：2015-07-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Murat Kerem Akarvardar

IPC: H01L27/088 ,  H01L29/78 ,  H01L21/84 ,  H01L29/66 ,  H01L29/06 ,  H01L29/165 ,  H01L21/8238

CPC classification number: H01L29/785 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0684 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795

Abstract: One illustrative method disclosed herein includes, among other things, oxidizing a lower portion of an initial fin structure to thereby define an isolation region that vertically separates an upper portion of the initial fin structure from a semiconducting substrate, performing a recess etching process to remove a portion of the upper portion of the initial fin structure so as to define a recessed fin portion, forming a replacement fin on the recessed fin portion so as to define a final fin structure comprised of the replacement fin and the recessed fin portion, and forming a gate structure around at least a portion of the replacement fin.

Abstract translation: 本文公开的一种说明性方法包括氧化初始鳍结构的下部，从而限定将初始鳍结构的上部与半导体衬底垂直分离的隔离区，执行凹陷蚀刻工艺以去除 初始翅片结构的上部的一部分，以便限定一个凹入的翅片部分，在该凹入的翅片部分上形成一个替换翅片，以便限定由替换翅片和该凹入的翅片部分组成的最终翅片结构， 围绕替换翅片的至少一部分的门结构。

公开(公告)号：US09343300B1

公开(公告)日：2016-05-17

申请号：US14686857

申请日：2015-04-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Michael Hargrove ,  Jody A. Fronheiser ,  Murat Kerem Akarvardar

IPC: H01L21/336 ,  H01L21/02 ,  H01L29/66 ,  H01L21/324 ,  H01L29/167 ,  H01L21/311 ,  H01L21/8234 ,  H01L21/225

CPC classification number: H01L29/66636 ,  H01L21/02579 ,  H01L21/02694 ,  H01L21/2251 ,  H01L21/2257 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/165 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7848

Abstract: The present disclosure is directed to forming relatively abrupt junctions between the channel region and source/drain regions of a PMOS transistor device with a germanium-containing channel region. A liner layer is formed in previously formed source/drain cavities prior to the formation of epi semiconductor material in the source/drain cavities above the liner layer. The materials for the liner layer and, particularly, the concentration of germanium (if any is present) are adjusted relative to the germanium concentration in the channel region and the epi source/drain material such that, during an anneal process, dopant materials (e.g., boron) that diffuse from the source/drain region during the anneal process tend to accumulate in or near the liner layer.

Abstract translation: 本公开涉及在具有含锗沟道区的PMOS晶体管器件的沟道区域和源极/漏极区域之间形成相对突然的结。 在预先形成的源/漏腔之前，在衬层之上的源极/漏极腔中形成外延半导体材料之前形成衬层。 用于衬里层的材料，特别是锗的浓度（如果有的话）相对于沟道区域和外延源/漏极材料中的锗浓度进行调节，使得在退火过程期间，掺杂剂材料（例如 ，硼）在退火工艺期间从源极/漏极区扩散倾向于积聚在衬里层中或其附近。

公开(公告)号：US20160118251A1

公开(公告)日：2016-04-28

申请号：US14525351

申请日：2014-10-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Jody A. Fronheiser ,  Murat Kerem Akarvardar

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L21/324 ,  H01L21/265

CPC classification number: H01L21/02532 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02579 ,  H01L21/02664 ,  H01L21/18 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: One illustrative method disclosed herein includes, among other things, performing first and second in situ doping, epitaxial deposition processes to form first and second layers of in situ doped epi semiconductor material, respectively, above a semiconductor substrate, wherein one of the first and second layers has a high level of germanium and a low level of P-type dopant material and the other of the first and second layers has a low level of germanium and a high level of P-type dopant material, and performing a mixing thermal anneal process on the first and second layers so as to form the final silicon germanium material having a high level of germanium and a high level of P-type dopant material.

Abstract translation: 本文中公开的一种说明性方法包括进行第一和第二原位掺杂，外延沉积工艺以分别在半导体衬底之上形成第一和第二层原位掺杂的外延半导体材料，其中第一和第二 层具有高水平的锗和低水平的P型掺杂剂材料，并且第一和第二层中的另一层具有低水平的锗和高水平的P型掺杂剂材料，并且进行混合热退火工艺 在第一和第二层上形成具有高水平的锗和高水平的P型掺杂剂材料的最终硅锗材料。

公开(公告)号：US09324790B2

公开(公告)日：2016-04-26

申请号：US14083571

申请日：2013-11-19

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc. ,  Renesas Electronics Corporation

Inventor： Murat Kerem Akarvardar ,  Steven John Bentley ,  Kangguo Cheng ,  Bruce B. Doris ,  Jody Fronheiser ,  Ajey Poovannummoottil Jacob ,  Ali Khakifirooz ,  Toshiharu Nagumo

IPC: H01L21/762 ,  H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/092

CPC classification number: H01L29/0653 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/785

Abstract: A method of forming a semiconductor structure includes forming a first isolation region between fins of a first group of fins and between fins of a second group of fins. The first a second group of fins are formed in a bulk semiconductor substrate. A second isolation region is formed between the first group of fins and the second group of fins, the second isolation region extends through a portion of the first isolation region such that the first and second isolation regions are in direct contact and a height above the bulk semiconductor substrate of the second isolation region is greater than a height above the bulk semiconductor substrate of the first isolation region.

Abstract translation: 形成半导体结构的方法包括在第一组鳍片的翅片之间以及在第二组鳍片的翅片之间形成第一隔离区域。 第一组翅片形成在体半导体衬底中。 第二隔离区域形成在第一散热片组和第二散热片组之间，第二隔离区域延伸穿过第一隔离区域的一部分，使得第一隔离区域和第二隔离区域直接接触并且高于主体 第二隔离区域的半导体衬底大于第一隔离区域的体半导体衬底上方的高度。

公开(公告)号：US09324617B1

公开(公告)日：2016-04-26

申请号：US14715050

申请日：2015-05-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Murat Kerem Akarvardar

IPC: H01L21/76 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/306 ,  H01L21/762 ,  H01L29/10

CPC classification number: H01L29/1033 ,  H01L21/02381 ,  H01L21/02428 ,  H01L21/02532 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886

Abstract: One method disclosed herein includes forming a virtual substrate by forming a sacrificial semiconductor material in a trench between a plurality of silicon fin structures formed in a bulk silicon substrate, forming a layer of silicon above the silicon fin structures and the sacrificial semiconductor material, performing at least one etching process to selectively remove the sacrificial semiconductor material relative to the silicon fin structures and the layer of silicon so as to define a cavity, forming a non-sacrificial semiconductor material on the layer of silicon and forming a layer of strained channel semiconductor material above the non-sacrificial semiconductor material positioned above the upper surface of the layer of silicon.

Abstract translation: 本文公开的一种方法包括通过在形成在体硅衬底中的多个硅鳍结构之间的沟槽中形成牺牲半导体材料来形成虚拟衬底，在硅鳍结构之上形成硅层和牺牲半导体材料，在 至少一个蚀刻工艺，以相对于硅鳍结构和硅层选择性地去除牺牲半导体材料，以便限定空腔，在硅层上形成非牺牲半导体材料并形成应变通道半导体材料层 在位于硅层的上表面之上的非牺牲半导体材料之上。

公开(公告)号：US09312387B2

公开(公告)日：2016-04-12

申请号：US14069955

申请日：2013-11-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Murat Kerem Akarvardar ,  Michael Hargrove ,  Ruilong Xie

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L29/785 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/66795

Abstract: Disclosed are methods and devices that involve formation of alternating layers of different semiconductor materials in the channel region of FinFET devices. The methods and devices disclosed herein involve forming a doped silicon substrate fin and thereafter forming a layer of silicon/germanium around the substrate fin. The methods and devices also include forming a gate structure around the layer of silicon/germanium using gate first or gate last techniques.

Abstract translation: 公开了涉及在FinFET器件的沟道区域中形成不同半导体材料的交替层的方法和器件。 本文公开的方法和装置包括形成掺杂的硅衬底鳍片，然后在衬底鳍片周围形成硅/锗层。 所述方法和装置还包括使用栅极第一或栅极末端技术在硅/锗层周围形成栅极结构。

公开(公告)号：US09305846B2

公开(公告)日：2016-04-05

申请号：US14599873

申请日：2015-01-19

Applicant: GLOBALFOUNDRIES INC. ,  International Business Machines Corporation ,  Renesas Electronics Corporation

Inventor： Ajey Poovannummoottil Jacob ,  Murat Kerem Akarvardar ,  Steven Bentley ,  Toshiharu Nagumo ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz

IPC: H01L21/762 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/761 ,  H01L21/02 ,  H01L21/266 ,  H01L29/78

CPC classification number: H01L21/823821 ,  H01L21/02227 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/266 ,  H01L21/3086 ,  H01L21/761 ,  H01L21/76224 ,  H01L21/823878 ,  H01L29/0646 ,  H01L29/66795 ,  H01L29/7851

Abstract: Embodiments herein provide approaches for device isolation in a complimentary metal-oxide fin field effect transistor. Specifically, a semiconductor device is formed with a retrograde doped layer over a substrate to minimize a source to drain punch-through leakage. A set of replacement fins is formed over the retrograde doped layer, each of the set of replacement fins comprising a high mobility channel material (e.g., silicon, or silicon-germanium). The retrograde doped layer may be formed using an in situ doping process or a counter dopant retrograde implant. The device may further include a carbon liner positioned between the retrograde doped layer and the set of replacement fins to prevent carrier spill-out to the replacement fins.

Abstract translation: 本文的实施例提供了在互补金属氧化物鳍片场效应晶体管中的器件隔离的方法。 具体地，半导体器件在衬底上形成有逆向掺杂层以最小化源极到漏极穿通泄漏。 在逆向掺杂层上形成一组替代翅片，该组替换鳍片中的每一个包括高迁移率通道材料（例如，硅或硅 - 锗）。 逆向掺杂层可以使用原位掺杂工艺或反掺杂剂逆向植入来形成。 该装置还可以包括位于逆向掺杂层和该替代翅片组之间的碳衬垫，以防止载体溢出到置换翅片。

公开(公告)号：US20160027895A1

公开(公告)日：2016-01-28

申请号：US14341000

申请日：2014-07-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Murat Kerem Akarvardar ,  Ajey Poovannummoottil Jacob

IPC: H01L29/66 ,  H01L21/02

CPC classification number: H01L29/1054 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7854

Abstract: One illustrative method disclosed herein includes, among other things, forming a sacrificial fin structure above a semiconductor substrate, forming a layer of insulating material around the sacrificial fin structure, removing the sacrificial fin structure so as to define a replacement fin cavity in the layer of insulating material that exposes an upper surface of the substrate, forming a replacement fin in the replacement fin cavity on the exposed upper surface of the substrate, recessing the layer of insulating material, and forming a gate structure around at least a portion of the replacement fin exposed above the recessed layer of insulating material.

Abstract translation: 本文公开的一种说明性方法包括在半导体衬底之上形成牺牲鳍结构，在牺牲鳍结构周围形成绝缘材料层，去除牺牲鳍结构，以便在 绝缘材料，其暴露衬底的上表面，在所述衬底的暴露的上表面上的替换翅片腔中形成替换翅片，使所述绝缘材料层凹陷，以及在所述替换鳍片的至少一部分周围形成栅极结构 暴露在绝缘材料的凹陷层上方。

公开(公告)号：US20150372080A1

公开(公告)日：2015-12-24

申请号：US14839378

申请日：2015-08-28

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc. ,  RENESAS ELECTRONICS CORPORATION

Inventor： Murat Kerem Akarvardar ,  Steven John Bentley ,  Kangguo Cheng ,  Bruce B. Doris ,  Jody Fronheiser ,  Ajey Poovannummoottil Jacob ,  Ali Khakifirooz ,  Toshiharu Nagumo

IPC: H01L29/06 ,  H01L27/092

CPC classification number: H01L29/0653 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/785

Abstract: A method of forming a semiconductor structure includes forming a first isolation region between fins of a first group of fins and between fins of a second group of fins. The first a second group of fins are formed in a bulk semiconductor substrate. A second isolation region is formed between the first group of fins and the second group of fins, the second isolation region extends through a portion of the first isolation region such that the first and second isolation regions are in direct contact and a height above the bulk semiconductor substrate of the second isolation region is greater than a height above the bulk semiconductor substrate of the first isolation region.

Abstract translation: 形成半导体结构的方法包括在第一组鳍片的翅片之间以及在第二组鳍片的翅片之间形成第一隔离区域。 第一组翅片形成在体半导体衬底中。 第二隔离区域形成在第一散热片组和第二散热片组之间，第二隔离区域延伸穿过第一隔离区域的一部分，使得第一隔离区域和第二隔离区域直接接触并且高于主体 第二隔离区域的半导体衬底大于第一隔离区域的体半导体衬底上方的高度。