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公开(公告)号：US09910827B2
公开(公告)日：2018-03-06
申请号：US15201040
申请日：2016-07-01
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Naveen Muralimanohar , Ben Feinberg , Ali Shafiee-Ardestani
Abstract: Examples herein relate to circuits for computing vector-matrix multiplications involving negative values. A first memory crossbar array may be mapped to a first matrix which includes the positive values of an input matrix. A second memory crossbar array may be mapped to a second matrix which includes the negative values of the input matrix. An analog-to-digital converter may generate digital intermediate multiplication results based on analog results computed by the memory crossbar arrays. The digital intermediate multiplication results may include an intermediate result corresponding to a multiplication of each of the first vector and second vector with each of the first matrix and the second matrix. A controller may aggregate the digital intermediate results to generate a combined multiple result that represents the vector-matrix multiplication of the input vector and the input matrix.
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公开(公告)号：US09773547B2
公开(公告)日：2017-09-26
申请号：US15113914
申请日：2014-01-31
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Richard H. Henze , Naveen Muralimanohar , Yoocharn Jeon , Martin Foltin , Erik Ordentlich , Gregg B. Lesartre , R. Stanley Williams
CPC classification number: G11C13/004 , G11C5/025 , G11C11/005 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0069 , G11C2213/71 , G11C2213/72 , G11C2213/77 , G11C2213/79 , H01L23/528 , H01L27/2463 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/14 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/147
Abstract: A non-volatile memory device with multiple latency tiers includes at least two crossbar memory arrays, each crossbar memory array comprising a number of memory cells, each memory cell connected to a word line and a bit line at a cross point. The crossbar memory arrays each have a different latency. The crossbar memory arrays are formed on a single die.
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公开(公告)号：US09767901B1
公开(公告)日：2017-09-19
申请号：US15245607
申请日：2016-08-24
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Amit S. Sharma , Gary Gibson , Naveen Muralimanohar , Martin Foltin , Greg Astfalk
CPC classification number: G11C13/0069 , G11C13/003 , G11C13/0033 , G11C13/0097 , G11C2013/0073 , G11C2213/15 , G11C2213/72 , G11C2213/74 , G11C2213/76
Abstract: An integrated circuit is provided. In an example, the integrated circuit includes a first address line, a selector device electrically coupled to the first address lines, and a memory device electrically coupled between the selector device and a second address line. The selector device has a first I-V response in a first current direction and a second I-V response in a second current direction that is different from the first I-V response.
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公开(公告)号：US09710335B2
公开(公告)日：2017-07-18
申请号：US14785421
申请日：2013-07-31
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Doe Hyun Yoon , Terence P. Kelly , Jichuan Chang , Naveen Muralimanohar , Robert Schreiber , Parthasarathy Ranganathan
CPC classification number: G06F11/1451 , G06F3/0614 , G06F3/0628 , G06F11/1072 , G06F11/1435 , G06F11/1471 , G06F2201/84 , G11C29/52
Abstract: According to an example, versioned memory implementation may include comparing a global memory version to a block memory version. The global memory version may correspond to a plurality of memory blocks, and the block memory version may correspond to one of the plurality of memory blocks. A subblock-bit-vector (SBV) corresponding to a plurality of subblocks of the one of the plurality of memory blocks may be evaluated. Based on the comparison and the evaluation, a determination may be made as to which level in a cell of one of the plurality of subblocks of the one of the plurality of memory blocks checkpoint data is stored.
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