公开(公告)号：US5587782A

公开(公告)日：1996-12-24

申请号：US394837

申请日：1995-02-27

申请人： Akiyoshi Johdai ,  Akira Ohhata ,  Hiroki Yamashita ,  Hirokazu Matsuo ,  Yoshihito Hirano

发明人： Akiyoshi Johdai ,  Akira Ohhata ,  Hiroki Yamashita ,  Hirokazu Matsuo ,  Yoshihito Hirano

IPC分类号： B65H5/02 ,  B65H7/20 ,  G03G15/00

CPC分类号： G03G15/60 ,  G03G2215/00185 ,  G03G2215/0032 ,  Y10S271/902

摘要： A copying machine having a two-in-one copying mode has a pickup roller 65, a separating roller 75, a register roller 90, a conveyor belt 95 and a pinch roller 101. The pickup roller 65 and the separating roller 75 feed a document toward a glass platen 29 one by one to stop the document at a first-out position. The register roller 90 conveys the document fed by the pickup roller 65 and the separating roller 75 onto the glass platen. The conveyor belt 95 conveys the document conveyed by the register roller 90 along the glass platen 29 until a rear end of the document reaches a predetermined switch-back position, then conveys the document in the opposite direction to retreat a predetermined distance, and then conveys the document as well as a succeeding document stopped at the first-out position such that a front end of the document situated on a downstream side of the document conveying direction may be aligned with an exposure reference SP, and then discharges the documents to the downstream side of the document conveying direction after exposure. The pinch roller 101 conveys the documents discharged by the conveyor belt 95 from the glass platen 29 to a discharge section 115.

摘要翻译： 具有二合一复印模式的复印机具有拾取辊65，分离辊75，对准辊90，传送带95和压紧辊101.拾取辊65和分离辊75供给文件 朝着玻璃台板29一个接一个地在原来的位置停止文件。 定位辊90将由拾取辊65和分离辊75馈送的原稿传送到玻璃台板上。 传送带95沿着玻璃压板29传送由对准辊90所传送的文件，直到文件的后端到达预定的关闭位置，然后沿相反方向传送文件以退回预定距离，然后传送 文档以及后续文件在首先位置停止，使得位于文件传送方向的下游侧的文档的前端可以与曝光参考SP对齐，然后将文档排出到下游 曝光后文件传送方向的一侧。 夹送辊101将由传送带95排出的文件从玻璃压板29传送到排出部115。

公开(公告)号：US5281865A

公开(公告)日：1994-01-25

申请号：US797922

申请日：1991-11-26

申请人： Hiroki Yamashita ,  Hiroyuki Itoh ,  Hirotoshi Tanaka ,  Atsumi Kawata ,  Kenji Nagai ,  Kazuhiro Yoshihara ,  Ichiro Imaizumi

发明人： Hiroki Yamashita ,  Hiroyuki Itoh ,  Hirotoshi Tanaka ,  Atsumi Kawata ,  Kenji Nagai ,  Kazuhiro Yoshihara ,  Ichiro Imaizumi

IPC分类号： H03K3/037 ,  H03K3/356 ,  H03K19/094 ,  H03K17/16 ,  H03K3/289

CPC分类号： H03K3/356026 ,  H03K19/09429 ,  H03K3/037

摘要： A flip-flop circuit receives a pair of complementary data signals, then outputs complementary signals corresponding to the pair of complementary data signals. The pair of data signals are also supplied to a driving gate means which outputs a signal corresponding to at least one data signal of the pair of data signals supplied thereto. The driving gate means also comprises at least one try-state gate controlled by a clock signal. An output signal of the driving gate means is held by a memory means, and also outputted as complementary output signals.

摘要翻译： 触发器电路接收一对互补数据信号，然后输出与该对互补数据信号对应的互补信号。 一对数据信号也被提供给驱动门装置，该驱动门装置输出与提供给它的一对数据信号的至少一个数据信号对应的信号。 驱动门装置还包括由时钟信号控制的至少一个试用状态门。 驱动门装置的输出信号由存储装置保持，并作为互补输出信号输出。

公开(公告)号：US08772880B2

公开(公告)日：2014-07-08

申请号：US13500636

申请日：2010-10-04

申请人： Koji Fukuda ,  Hiroki Yamashita

发明人： Koji Fukuda ,  Hiroki Yamashita

IPC分类号： H01L27/088

CPC分类号： H03K19/00384 ,  H01L27/0207 ,  H01L27/0629 ,  H01L27/0811 ,  H01L27/088

摘要： A high-speed semiconductor integrated circuit device is achieved by adjusting an offset voltage. For example, dummy NMOS transistors MND1 (MND1a and MND1b) and MND2 (MND2a and MND2b) are connected to drain outputs of NMOS transistors MN1 and MN2 operated according to differential input signals Din_p and Din_n, respectively. The MND1 is arranged adjacent to the MN1, and a source of the MND1a and a drain of the MN1 share a diffusion layer. The MND2 is arranged adjacent to the MN2, and a source of the MND2a and a drain of the MN2 share a diffusion layer. The MND1 and the MND2 function as dummy transistors for suppressing variations in process of the MN1 and the MN2 and, and besides, they also function as means for adjusting the offset voltage by appropriately applying an offset-amount setting signal OFST to each gate to provide a capacitor to either the MN1 or the MN2.

摘要翻译： 通过调整偏移电压来实现高速半导体集成电路器件。 例如，虚拟NMOS晶体管MND1（MND1a和MND1b）和MND2（MND2a和MND2b）分别连接到根据差分输入信号Din_p和Din_n操作的NMOS晶体管MN1和MN2的漏极输出。 MND1布置成与MN1相邻，并且MND1a的源极和MN1的漏极共享扩散层。 MND2被布置为与MN2相邻，并且MND2a的源极和MN2的漏极共享扩散层。 MND1和MND2用作用于抑制MN1和MN2的处理变化的虚拟晶体管，此外，它们还用作通过适当地向每个门施加偏移量设置信号OFST来调整偏移电压的装置，以提供 一个到MN1或MN2的电容器。

公开(公告)号：US08674725B2

公开(公告)日：2014-03-18

申请号：US13358324

申请日：2012-01-25

申请人： Hiroaki Kurahashi ,  Tomofumi Hokari ,  Takashi Muto ,  Goichi Ono ,  Hiroki Yamashita

发明人： Hiroaki Kurahashi ,  Tomofumi Hokari ,  Takashi Muto ,  Goichi Ono ,  Hiroki Yamashita

IPC分类号： H03K19/0175

CPC分类号： H03K19/018514

摘要： A transmitter circuit in which a driver circuit includes MOS transistors for bias voltage application, in which a driving current flows, cascode-connected to MOS transistors for differential signal input controlled by a voltage value of transmitted data signals, controlled by a voltage value of a bias voltage, and driver circuits include MOS transistors for bias voltage application, in which a driving current flows, cascode-connected to MOS transistors for differential signal input that is controlled by a voltage value of signals obtained by the transmitted data signals, connected to a load portion, and controlled by a voltage value of a bias voltage.

摘要翻译： 一种发射机电路，其中驱动电路包括用于偏压施加的MOS晶体管，其中驱动电流流动，共源共栅连接到MOS晶体管，用于由传输数据信号的电压值控制的差分信号输入，由电压值 偏置电压和驱动电路包括用于偏置电压施加的MOS晶体管，其中驱动电流流动，共源共栅连接到用于差分信号输入的MOS晶体管，该MOS晶体管由通过发送的数据信号获得的信号的电压值控制，连接到 负载部分，并由偏置电压的电压值控制。

公开(公告)号：US20110249980A1

公开(公告)日：2011-10-13

申请号：US13085470

申请日：2011-04-12

申请人： Takashi Takemoto ,  Hiroki Yamashita ,  Shinji Tsuji

发明人： Takashi Takemoto ,  Hiroki Yamashita ,  Shinji Tsuji

IPC分类号： H04B10/04

CPC分类号： H04B10/503 ,  H01L2224/16225 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01S5/02248 ,  H01L2924/00

摘要： An optical communication module and an optical communication device including the same are provided. For example, a first semiconductor chip on which a laser diode is formed and a second semiconductor chip on which a laser diode driver circuit, etc. for subjecting the laser diode to drive by current are formed are mounted on a package printed circuit board to be close to each other. Temperature detecting means is further formed on the second semiconductor chip (laser diode driver circuit, etc.). The temperature detecting means detects a temperature variation ΔT of the first semiconductor chip (laser diode) transmitted via a wiring in the package printed circuit board and controls the magnitude of the driving current of the laser diode driver circuit based on a detection result.

摘要翻译： 提供了一种光通信模块和包括该光通信模块的光通信设备。 例如，形成激光二极管的第一半导体芯片和形成激光二极管通过电流驱动的激光二极管驱动电路等的第二半导体芯片安装在封装印刷电路板上 彼此接近 温度检测装置还形成在第二半导体芯片（激光二极管驱动电路等）上。 温度检测装置检测通过封装印刷电路板中的布线传输的第一半导体芯片（激光二极管）的温度变化＆Dgr; T，并根据检测结果控制激光二极管驱动电路的驱动电流的大小。

公开(公告)号：US20100186096A1

公开(公告)日：2010-07-22

申请号：US12753273

申请日：2010-04-02

申请人： Satoru Wakao ,  Hiroki Yamashita

发明人： Satoru Wakao ,  Hiroki Yamashita

IPC分类号： G06F7/04 ,  G06F12/14

CPC分类号： H04N1/32128 ,  H04L9/3242 ,  H04L9/3247 ,  H04L2209/60 ,  H04N1/32112 ,  H04N2201/3233 ,  H04N2201/3242 ,  H04N2201/325

摘要： An image processing apparatus includes an alteration unit and a control unit. The alteration unit alters a first image file stored in a removable storage medium in order to generate a second image file. The control unit controls to store the second image file in the storage medium without deleting the first image file from the storage medium, if the first image file includes authentication data that is used to authenticate whether the first image file has been altered.

摘要翻译： 图像处理装置包括改变单元和控制单元。 改变单元改变存储在可移动存储介质中的第一图像文件，以便生成第二图像文件。 如果第一图像文件包括用于认证第一图像文件是否被改变的认证数据，则控制单元控制将第二图像文件存储在存储介质中而不从存储介质中删除第一图像文件。

公开(公告)号：US07742983B2

公开(公告)日：2010-06-22

申请号：US09775591

申请日：2001-02-05

申请人： Kazunori Ukigawa ,  Hiroki Yamashita

发明人： Kazunori Ukigawa ,  Hiroki Yamashita

IPC分类号： G06Q40/00

CPC分类号： G06Q30/06 ,  G06Q20/02 ,  G06Q20/04 ,  G06Q20/10 ,  G06Q20/102 ,  G06Q20/12 ,  G06Q20/385 ,  G06Q30/0601

摘要： An agent device is connected to a user device for browsing a merchant site, for selling products online and being served up on the Internet, the merchant site, and a server device of a credit-card company. In the case where an instruction of purchasing a product browsed by the user device is output, the instruction is sent to the agent device. The agent device extracts a credit card number of a credit card held by a user having purchased the product, and inquires of the server device of the credit card company whether the product is to be purchased with the credit card. As an inquiry result, in the case where the product can be purchased online with the credit card, the agent device sends an instruction that the user purchases the product online with the credit card.

摘要翻译： 代理设备连接到用于浏览商家站点的用户设备，用于在线上销售产品并在因特网，商家站点和信用卡公司的服务器设备上进行服务。 在输出由用户装置浏览的商品的指示的情况下，将指示发送给代理装置。 代理装置提取购买了该商品的用户持有的信用卡的信用卡号码，并向该信用卡公司的服务器装置询问是否用该信用卡购买该商品。 作为查询结果，在使用信用卡在线购买产品的情况下，代理设备发送用户使用信用卡在线购买产品的指令。

公开(公告)号：US20090231001A1

公开(公告)日：2009-09-17

申请号：US12320409

申请日：2009-01-26

申请人： Koji Fukuda ,  Hiroki Yamashita ,  Daisuke Hamano

发明人： Koji Fukuda ,  Hiroki Yamashita ,  Daisuke Hamano

IPC分类号： H03L7/00

CPC分类号： H03L7/08 ,  H04L7/0331

摘要： A signal recovery circuit capable of expanding the receive margin is provided. The signal recovery circuit comprises for example a clock generator unit CLK_GEN for generating the clock signals CLKa, CLKb, and CLKc, a window width control unit WW_CTL, and a clock data discriminator unit CD_JGE for generating a phase detector signal (EARLY, LATE) when for example a data signal Di pulse edge enters between the CLKa and CLKb, or between the CLKb and CLKc, and the clock generator unit. Along with exerting control based on these phase detection signals to maintain the mutual Phase differential of the overall phase of CLKa, CLKb, CLKc so as to prevent intrusion of the above described Di edge, the CLK_GEN also regulates the phase differential between CLKa and CLKb, and the phase differential between CLKb and CLKc based on a signal (Sww) from the WW_CTL.

摘要翻译： 提供了能够扩大接收余量的信号恢复电路。 信号恢复电路包括例如用于产生时钟信号CLKa，CLKb和CLKc的时钟发生器单元CLK_GEN，窗口宽度控制单元WW_CTL和用于产生相位检测器信号（EARLY，LATE）的时钟数据鉴别器单元CD_JGE 例如数据信号Di脉冲沿进入CLKa和CLKb之间，或在CLKb与CLKc之间进入时钟发生器单元。 随着基于这些相位检测信号进行控制以维持CLKa，CLKb，CLKc的总相位的相互相位差，以防止上述Di边缘的入侵，CLK_GEN还调节CLKa和CLKb之间的相位差， 以及基于来自WW_CTL的信号（Sww）的CLKb和CLKc之间的相位差。

公开(公告)号：US20080265973A1

公开(公告)日：2008-10-30

申请号：US12105586

申请日：2008-04-18

申请人： Hiroki Yamashita ,  Ryo Nemoto

发明人： Hiroki Yamashita ,  Ryo Nemoto

IPC分类号： H03L5/00

CPC分类号： H03K19/018557

摘要： A receiver circuit includes first and second constant current sources respectively connected to a pair of first and second receiving terminals to receive complementary current signals, a first NMOS transistor connected at a source thereof to the first receiving terminal and the first constant current source and connected at a drain thereof to a first power supply via a first output terminal and first load means, and a second NMOS transistor connected at a source thereof to the second receiving terminal and the second constant current source and connected at a drain thereof to the first power supply via a second output terminal and second load means.

摘要翻译： 接收器电路包括分别连接到一对第一和第二接收端子以接收互补电流信号的第一和第二恒定电流源，连接到其源极的第一NMOS晶体管与第一接收端子和第一恒定电流源连接， 其漏极经由第一输出端子和第一负载装置到第一电源，以及第二NMOS晶体管，其源极连接到第二接收端子和第二恒流源，并在其漏极处连接到第一电源 经由第二输出端子和第二负载装置。

公开(公告)号：US20080056342A1

公开(公告)日：2008-03-06

申请号：US11782705

申请日：2007-07-25

申请人： KOJI FUJUDA ,  Hidehiro Toyoda ,  Hiroki Yamashita

发明人： KOJI FUJUDA ,  Hidehiro Toyoda ,  Hiroki Yamashita

IPC分类号： H03H21/00

CPC分类号： G11B20/10009 ,  G11B20/10046 ,  G11B20/10194 ,  G11B20/10481 ,  G11B2220/2537

摘要： In pulse width control equalization, attention is paid to the existence of the symmetry of anteroposterior signals and thereby the size of a table in which the adjustment amount of an edge position is stored is reduced to the power of one-half. Pattern jitters caused by inter-symbol interference are suppressed. The pulse time span of each symbol is adjusted to an optimum pulse width determined by a calculating formula or search in a table in response to a code sequence to be transmitted. In the configuration wherein a table is used, the table to store an edge position adjustment amount wherein the row of the exclusive OR of two symbols located at positions symmetrical to each other before and after a center symbol now ready to be sent in the code sequence is used as a search key is made.

摘要翻译： 在脉冲宽度控制均衡中，注意前后信号的对称性的存在，从而将存储边缘位置的调整量的表的尺寸减小到二分之一的幂。 由符号间干扰引起的模式抖动被抑制。 每个符号的脉冲时间间隔被调整为由计算公式确定的最佳脉冲宽度或响应于要发送的代码序列在表中搜索。 在使用表格的结构中，存储边缘位置调整量的表，其中位于现在准备好以代码序列发送的中心符号之前和之后彼此对称的两个符号的异或的行 被用作搜索键。