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公开(公告)号：US20190043596A1
公开(公告)日：2019-02-07
申请号：US15838202
申请日：2017-12-11
Applicant: Intel Corporation
Inventor： Aliasgar S. Madraswala , Xin Guo , Ali Khakifirooz , Pranav Kalavade , Sagar Upadhyay
Abstract: Embodiments of the present disclosure may relate to a memory controller that may include a memory interface and a logic circuitry component coupled with the memory interface. In some embodiments, the logic circuitry component is to program one or more NAND cells of a multi-level NAND memory array via the memory interface with a first set of data in a first pass, determine a first temperature of the multi-level NAND memory array in association with the first pass, determine a second temperature of the multi-level NAND memory array, determine a temperature difference between the second temperature and the first temperature, and perform one or more operations based at least in part on a result of the determination of the temperature difference. Other embodiments may be described and/or claimed.
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公开(公告)号：US10141071B2
公开(公告)日：2018-11-27
申请号：US14998119
申请日：2015-12-26
Applicant: Intel Corporation
Inventor： Shantanu R. Rajwade , Pranav Kalavade
Abstract: Methods and apparatus related to predictive Count Fail Byte (CFBYTE) for non-volatile memory are described. In one embodiment, logic determines a number of memory cells of the non-volatile memory that would pass or fail verification in a current program loop. The logic determines the number of the memory cells based at least in part on information from a previous program loop. The previous program loop is executed prior to the current program loop. The logic causes inhibition of one or more verification pulses to be issued in the current program loop based on comparison of the information from the previous program loop and a threshold value. Other embodiments are also disclosed and claimed.
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Patent Agency Ranking
公开(公告)号：US10120751B2
公开(公告)日：2018-11-06
申请号：US14866291
申请日：2015-09-25
Applicant: INTEL CORPORATION
Inventor： Jawad B. Khan , Anand S. Ramalingam , Pranav Kalavade
Abstract: Examples may include techniques to recover data from a solid state drive (SSD) using exclusive OR (XOR) parity information. Data saved to non-volatile types of block-erasable memory such as NAND memory included in the SSD may be recovered via use of XOR parity information saved to types of write-in-place memory such as a 3-dimensional cross-point memory also included in the SSD.
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公开(公告)号：US20180088823A1
公开(公告)日：2018-03-29
申请号：US15280725
申请日：2016-09-29
Applicant: Intel Corporation
Inventor： Anand S. Ramalingam , Jawad B. Khan , Pranav Kalavade
CPC classification number: G06F3/0608 , G06F3/064 , G06F3/0652 , G06F3/0658 , G06F3/0659 , G06F3/0679 , G11C16/0483 , G11C16/16 , G11C16/3445
Abstract: Systems, apparatuses and methods may provide for initiating an erase of a block of non-volatile memory in response to an erase command, wherein the block includes a plurality of sub-blocks. Additionally, a failure of the erase with respect to a first subset of the plurality of sub-blocks may be tracked on an individual sub-block basis, wherein the erase is successful with respect to a second subset of the plurality of sub-blocks. In one example, use of the second subset of the plurality of sub-blocks is permitted, whereas use of the first subset of the plurality of sub-blocks is prevented.
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公开(公告)号：US09852065B1
公开(公告)日：2017-12-26
申请号：US15195328
申请日：2016-06-28
Applicant: Intel Corporation
Inventor： Shantanu R. Rajwade , Andrea D'alessandro , Pranav Kalavade , Violante Moschiano
CPC classification number: G06F12/0246 , G06F11/073 , G06F11/076 , G06F2212/2022 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3459 , G11C2211/5644
Abstract: In one embodiment, an apparatus comprises a storage device comprising a NAND flash memory. The storage device is to receive a write request from a computing host, the write request to specify data to be written to the NAND flash memory; perform a number of program loops to program the data into a plurality of cells of the NAND flash memory, wherein a program loop comprises application of a program voltage to a wordline of the memory to change the threshold voltage of at least one cell of the plurality of cells; and wherein the number of program loops is to be determined prior to receipt of the write request and based on a distribution of threshold voltages of the cells or determined based on tracking a number of program errors for only a portion of the plurality of cells.
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公开(公告)号：US20160372207A1
公开(公告)日：2016-12-22
申请号：US15183582
申请日：2016-06-15
Applicant: Intel Corporation
Inventor： Shantanu R. Rajwade , Pranav Kalavade , Neal R. Mielke , Krishna K. Parat , Shyam Sunder Raghunathan
CPC classification number: G11C16/3427 , G11C16/0483 , G11C16/08 , G11C16/10
Abstract: The inhibit voltage is a voltage applied to wordlines adjacent to a program wordline having a memory cell to write during the program operation. The inhibit voltage for a program operation can be ramped up during the program pulse. Instead of applying a constant high inhibit voltage that results in the initial boosted channel potential reducing drastically due to leakage, a system can start the inhibit voltage lower and ramp the inhibit voltage up during the program pulse. The ramping up can be a continuous ramp or in finite discrete steps during the program pulse. Such ramping of inhibit voltage can provide better tradeoff between program disturb and inhibit disturb.
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67.发明申请公开(公告)号：US20160087646A1
公开(公告)日：2016-03-24
申请号：US14490307
申请日：2014-09-18
Applicant: Intel Corporation
Inventor： Ravi H. Motwani , Pranav Kalavade
IPC: H03M7/02
Abstract: Described is an apparatus for converting binary data to ternary and back such that the apparatus comprises: a first look-up table (LUT) having a mapping of 19 binary bits to 12 ternary trits; and a first logic to receive a binary input and to convert the binary input to a ternary output according to the first LUT.
Abstract translation: 描述了一种用于将二进制数据转换为三进制和反向的装置，使得该装置包括：具有19个二进制位到12个三进制位映射的第一查找表（LUT） 以及接收二进制输入并根据第一LUT将二进制输入转换为三进制输出的第一逻辑。
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