公开(公告)号：US20160365385A1

公开(公告)日：2016-12-15

申请号：US15247710

申请日：2016-08-25

Applicant: INTEL CORPORATION

Inventor： Ravi PILLARISETTY ,  Brian S. DOYLE ,  Elijah V. KARPOV ,  David L. KENCKE ,  Uday SHAH ,  Charles C. KUO ,  Robert S. CHAU

IPC: H01L27/24 ,  H01L29/78 ,  H01L45/00 ,  H01L29/66

CPC classification number: H01L27/2436 ,  H01L29/66477 ,  H01L29/66568 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1616 ,  H01L2029/7858

Abstract: An insulating layer is deposited over a transistor structure. The transistor structure comprises a gate electrode over a device layer on a substrate. The transistor structure comprises a first contact region and a second contact region on the device layer at opposite sides of the gate electrode. A trench is formed in the first insulating layer over the first contact region. A metal-insulator phase transition material layer with a S-shaped IV characteristic is deposited in the trench or in the via of the metallization layer above on the source side.

公开(公告)号：US20160308041A1

公开(公告)日：2016-10-20

申请号：US15036780

申请日：2013-12-23

Applicant: INTEL CORPORATION

Inventor： Han Wui Then ,  Robert S. CHAU ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC ,  Benjamin CHU-KUNG ,  Seung Hoon Hoon SUNG ,  Sanaz K. GARDNER ,  Ravi PILLARISETTY

IPC: H01L29/78 ,  H01L29/20 ,  H01L29/66 ,  H01L29/32 ,  H01L29/34 ,  H01L29/08 ,  H01L29/06 ,  H01L29/205

CPC classification number: H01L29/785 ,  H01L21/8252 ,  H01L21/84 ,  H01L27/0605 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/32 ,  H01L29/34 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/66795

Abstract: Techniques are disclosed for forming a GaN transistor on a semiconductor substrate. An insulating layer forms on top of a semiconductor substrate. A trench, filled with a trench material comprising a III-V semiconductor material, forms through the insulating layer and extends into the semiconductor substrate. A channel structure, containing III-V material having a defect density lower than the trench material, forms directly on top of the insulating layer and adjacent to the trench. A source and drain form on opposite sides of the channel structure, and a gate forms on the channel structure. The semiconductor substrate forms a plane upon which both GaN transitors and other transistors can form.

Abstract translation: 公开了在半导体衬底上形成GaN晶体管的技术。 在半导体衬底的顶部形成绝缘层。 填充有包含III-V族半导体材料的沟槽材料的沟槽通过绝缘层形成并延伸到半导体衬底中。 含有缺陷密度低于沟槽材料的III-V材料的沟道结构直接形成在绝缘层的顶部并且与沟槽相邻。 在沟道结构的相对侧上的源极和漏极形式，以及在沟道结构上形成栅极。 半导体衬底形成可以形成GaN移动器和其它晶体管的平面。

公开(公告)号：US20160293601A1

公开(公告)日：2016-10-06

申请号：US15037618

申请日：2013-12-27

Applicant: INTEL CORPORATION

Inventor： Prashant MAJHI ,  Niloy MUKHERJEE ,  Ravi PILLARISETTY ,  Willy RACHMADY ,  Robert S. CHAU

IPC: H01L27/092 ,  H01L29/165 ,  H01L29/06 ,  H01L29/10 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/78669 ,  H01L29/78684

Abstract: An apparatus comprising a complimentary metal oxide semiconductor (CMOS) inverter including an n-channel metal oxide semiconductor field effect transistor (MOSFET); and a p-channel MOSFET, wherein a material of a channel in the n-channel MOSFET and a material of a channel in the p-channel MOSFET is subject to a bi-axial tensile strain. A method including forming an n-channel metal oxide semiconductor field effect transistor (MOSFET); forming a p-channel MOSFET; and connecting the gate electrodes and the drain regions of the n-channel MOSFET and the p-channel MOSFET, wherein a material of the channel in the n-channel MOSFET and a material of the channel in the p-channel MOSFET is subject to a bi-axial tensile strain.

Abstract translation: 一种包括具有n沟道金属氧化物半导体场效应晶体管（MOSFET）的互补金属氧化物半导体（CMOS）反相器的装置; 以及p沟道MOSFET，其中n沟道MOSFET中的沟道材料和p沟道MOSFET中的沟道的材料经受双轴向拉伸应变。 一种包括形成n沟道金属氧化物半导体场效应晶体管（MOSFET）的方法; 形成p沟道MOSFET; 以及连接n沟道MOSFET和p沟道MOSFET的栅电极和漏极区，其中n沟道MOSFET中的沟道的材料和p沟道MOSFET中的沟道的材料受到 双向拉伸应变。

公开(公告)号：US20160064512A1

公开(公告)日：2016-03-03

申请号：US14936609

申请日：2015-11-09

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Robert CHAU ,  Benjamin CHU-KUNG ,  Gilbert DEWEY ,  Jack KAVALIEROS ,  Matthew METZ ,  Niloy MUKHERJEE ,  Ravi PILLARISETTY ,  Marko RADOSAVLJEVIC

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/06

CPC classification number: H01L29/158 ,  B82Y10/00 ,  H01L21/02603 ,  H01L23/66 ,  H01L27/0605 ,  H01L27/0886 ,  H01L29/045 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66469 ,  H01L29/66522 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/778 ,  H01L29/7786 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78681 ,  H01L29/78696 ,  H01L2223/6677 ,  Y10S977/938

Abstract: A group III-N nanowire is disposed on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first group III-N material, a source region electrically coupled with a first end of the channel region, and a drain region electrically coupled with a second end of the channel region. A second group III-N material on the first group III-N material serves as a charge inducing layer, and/or barrier layer on surfaces of nanowire. A gate insulator and/or gate conductor coaxially wraps completely around the nanowire within the channel region. Drain and source contacts may similarly coaxially wrap completely around the drain and source regions.

公开(公告)号：US20150318375A1

公开(公告)日：2015-11-05

申请号：US14752365

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Niloy MUKHERJEE ,  Niti GOEL ,  Sanaz Kabehie GARDNER ,  Seung Hoon SUNG ,  Ravi PILLARISETTY ,  Robert S. CHAU

IPC: H01L29/66 ,  H01L29/205 ,  H01L21/223 ,  H01L21/02 ,  H01L29/08 ,  H01L21/265 ,  H01L29/20 ,  H01L21/311

CPC classification number: H01L29/7784 ,  H01L21/0254 ,  H01L21/2233 ,  H01L21/2236 ,  H01L21/2654 ,  H01L21/26546 ,  H01L21/31111 ,  H01L21/31144 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/207 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787

Abstract: Embodiments include high electron mobility transistors (HEMT). In embodiments, a gate electrode is spaced apart by different distances from a source and drain semiconductor region to provide high breakdown voltage and low on-state resistance. In embodiments, self-alignment techniques are applied to form a dielectric liner in trenches and over an intervening mandrel to independently define a gate length, gate-source length, and gate-drain length with a single masking operation. In embodiments, III-N HEMTs include fluorine doped semiconductor barrier layers for threshold voltage tuning and/or enhancement mode operation.

Abstract translation: 实施例包括高电子迁移率晶体管（HEMT）。 在实施例中，栅电极与源极和漏极半导体区间隔开不同的距离以提供高击穿电压和低导通状态电阻。 在实施例中，应用自对准技术以在沟槽中和在中间心轴上形成电介质衬垫，以通过单个掩蔽操作独立地限定栅极长度，栅极源长度和栅极 - 漏极长度。 在实施例中，III-N HEMT包括用于阈值电压调谐和/或增强模式操作的氟掺杂半导体势垒层。