公开(公告)号：US20160308041A1

公开(公告)日：2016-10-20

申请号：US15036780

申请日：2013-12-23

Applicant: INTEL CORPORATION

Inventor： Han Wui Then ,  Robert S. CHAU ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC ,  Benjamin CHU-KUNG ,  Seung Hoon Hoon SUNG ,  Sanaz K. GARDNER ,  Ravi PILLARISETTY

IPC: H01L29/78 ,  H01L29/20 ,  H01L29/66 ,  H01L29/32 ,  H01L29/34 ,  H01L29/08 ,  H01L29/06 ,  H01L29/205

CPC classification number: H01L29/785 ,  H01L21/8252 ,  H01L21/84 ,  H01L27/0605 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/32 ,  H01L29/34 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/66795

Abstract: Techniques are disclosed for forming a GaN transistor on a semiconductor substrate. An insulating layer forms on top of a semiconductor substrate. A trench, filled with a trench material comprising a III-V semiconductor material, forms through the insulating layer and extends into the semiconductor substrate. A channel structure, containing III-V material having a defect density lower than the trench material, forms directly on top of the insulating layer and adjacent to the trench. A source and drain form on opposite sides of the channel structure, and a gate forms on the channel structure. The semiconductor substrate forms a plane upon which both GaN transitors and other transistors can form.

Abstract translation: 公开了在半导体衬底上形成GaN晶体管的技术。 在半导体衬底的顶部形成绝缘层。 填充有包含III-V族半导体材料的沟槽材料的沟槽通过绝缘层形成并延伸到半导体衬底中。 含有缺陷密度低于沟槽材料的III-V材料的沟道结构直接形成在绝缘层的顶部并且与沟槽相邻。 在沟道结构的相对侧上的源极和漏极形式，以及在沟道结构上形成栅极。 半导体衬底形成可以形成GaN移动器和其它晶体管的平面。

公开(公告)号：US20160056244A1

公开(公告)日：2016-02-25

申请号：US14779257

申请日：2013-06-28

Applicant: INTEL CORPORATION

Inventor： Sansaptak DASGUPTA ,  Han Wui THEN ,  Sanaz K. GARDNER ,  Benjamin CHU-KUNG ,  Marko RADOSAVLJEVIC ,  Seung Hoon SUNG ,  Robert S. CHAU

IPC: H01L29/205 ,  H01L29/04 ,  H01L21/324 ,  H01L29/06 ,  H01L21/02 ,  H01L21/308

CPC classification number: H01L29/205 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02538 ,  H01L21/0254 ,  H01L21/02587 ,  H01L21/02609 ,  H01L21/02639 ,  H01L21/30608 ,  H01L21/308 ,  H01L21/324 ,  H01L21/76224 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0684

Abstract: A fin over an insulating layer on a substrate having a first crystal orientation is modified to form a surface aligned along a second crystal orientation. A device layer is deposited over the surface of the fin aligned along the second crystal orientation.

Abstract translation: 在具有第一晶体取向的基板上的绝缘层上的鳍被修改以形成沿着第二晶体取向对准的表面。 器件层沉积在沿着第二晶体取向对准的鳍片的表面上。

公开(公告)号：US20150108496A1

公开(公告)日：2015-04-23

申请号：US14581722

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC ,  Benjamin CHU-KUNG ,  Sanaz GARDNER ,  Seung Hoon SUNG ,  Robert S. Chau

IPC: H01L27/12 ,  H01L29/201 ,  H01L29/06 ,  H01L21/285 ,  H01L29/66 ,  H01L21/84 ,  H01L21/02 ,  H01L29/20 ,  H01L29/778

CPC classification number: H01L29/2003 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/0228 ,  H01L21/0254 ,  H01L21/283 ,  H01L21/28575 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/201 ,  H01L29/42356 ,  H01L29/66462 ,  H01L29/66795 ,  H01L29/7787 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/802

Abstract: A III-N semiconductor channel is formed on a III-N transition layer formed on a (111) or (110) surface of a silicon template structure, such as a fin sidewall. In embodiments, the silicon fin has a width comparable to the III-N epitaxial film thicknesses for a more compliant seeding layer, permitting lower defect density and/or reduced epitaxial film thickness. In embodiments, a transition layer is GaN and the semiconductor channel comprises Indium (In) to increase a conduction band offset from the silicon fin. In other embodiments, the fin is sacrificial and either removed or oxidized, or otherwise converted into a dielectric structure during transistor fabrication. In certain embodiments employing a sacrificial fin, the III-N transition layer and semiconductor channel is substantially pure GaN, permitting a breakdown voltage higher than would be sustainable in the presence of the silicon fin.

Abstract translation: III-N半导体沟道形成在形成于诸如翅片侧壁的硅模板结构的（111）或（110）表面上的III-N过渡层上。 在实施例中，硅鳍具有与更适应的种子层的III-N外延膜厚度相当的宽度，允许更低的缺陷密度和/或降低的外延膜厚度。 在实施例中，过渡层是GaN，并且半导体沟道包括铟（In）以增加从硅片的导带偏移。 在其它实施例中，鳍是牺牲性的，并且在晶体管制造期间被去除或氧化，或以其它方式转换为电介质结构。 在采用牺牲散热片的某些实施例中，III-N过渡层和半导体通道是基本上纯的GaN，允许击穿电压高于在硅片存在时可持续的击穿电压。