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    Hierarchical cache structure and handling thereof
    64.
    发明授权
    Hierarchical cache structure and handling thereof 有权
    层次缓存结构及其处理

    公开(公告)号：US09563568B2

    公开(公告)日：2017-02-07

    申请号：US14935909

    申请日：2015-11-09

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Christian Habermann ,  Christian Jacobi ,  Martin Recktenwald ,  Hans-Werner Tast

    IPC: G06F12/0811 ,  G06F12/08 ,  G06F13/00

    CPC classification number: G06F12/0897 ,  G06F12/0811 ,  G06F2212/1024 ,  G06F2212/604

    Abstract: A hierarchical cache structure includes at least one real indexed higher level cache with a directory and a unified cache array for data and instructions, and at least two lower level caches, each split in an instruction cache and a data cache. An instruction cache of a split real indexed second level cache includes a directory and a corresponding cache array connected to the real indexed third level cache. A data cache of the split second level cache includes a directory connected to the third level cache. An instruction cache of a split virtually indexed first level cache is connected to the second level instruction cache. A cache array of a data cache of the first level cache is connected to the cache array of the second level instruction cache and to the cache array of the third level cache. A directory of the first level data cache is connected to the second level instruction cache directory and to the third level cache directory.

    Abstract translation: 分级缓存结构包括至少一个具有目录的真实索引高级缓存和用于数据和指令的统一高速缓存阵列，以及至少两个较低级别的高速缓存，每个高速缓存分离在指令高速缓存和数据高速缓存中。 分割的实际索引的二级高速缓存的指令高速缓存包括连接到实际索引的第三级高速缓存的目录和对应的高速缓存阵列。 分离的第二级高速缓存的数据高速缓存包括连接到第三级高速缓存的目录。 分割的虚拟索引的第一级高速缓存的指令高速缓存连接到第二级指令高速缓存。 第一级高速缓存的数据高速缓存的高速缓存阵列连接到第二级指令高速缓存的高速缓存阵列和第三级高速缓存的高速缓存阵列。 第一级数据高速缓存的目录连接到第二级指令高速缓存目录和第三级缓存目录。

    SPECULATIVE BRANCH HANDLING FOR TRANSACTION ABORT
    66.
    发明申请
    SPECULATIVE BRANCH HANDLING FOR TRANSACTION ABORT 有权
    用于交易中止的分行分支处理

    公开(公告)号：US20160350125A1

    公开(公告)日：2016-12-01

    申请号：US15244741

    申请日：2016-08-23

    Applicant: International Business Machines Corporation

    Inventor： Michael Billeci ,  James J. Bonanno ,  Adam B. Collura ,  Christian Jacobi ,  Anthony Saporito ,  Timothy J. Slegel

    IPC: G06F9/38 ,  G06F9/46 ,  G06F9/30

    CPC classification number: G06F9/3844 ,  G06F9/30058 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3865 ,  G06F9/466 ,  G06F9/467

    Abstract: Embodiments relate to speculative branch handling for transaction abort. An aspect includes detecting a beginning of a current execution of a transaction. Another aspect includes, based on detecting the beginning of the transaction, disabling speculative execution based on branch prediction of an initial branch instruction of the transaction, wherein the initial branch instruction branches to two possible paths, and wherein a first path of the two possible paths comprises an abort handler. Another aspect includes disabling updating of a history table for the initial branch instruction.

    Abstract translation: 实施例涉及事务中止的推测性分支处理。 一方面包括检测交易的当前执行的开始。 另一方面包括：基于检测事务的开始，基于事务的初始分支指令的分支预测来禁用推测执行，其中初始分支指令分支到两个可能的路径，并且其中两个可能路径的第一路径 包括中止处理程序。 另一方面包括禁用更新初始分支指令的历史表。

    Sharing program interrupt logic in a multithreaded processor
    67.
    发明授权
    Sharing program interrupt logic in a multithreaded processor 有权
    在多线程处理器中共享程序中断逻辑

    公开(公告)号：US09507602B2

    公开(公告)日：2016-11-29

    申请号：US15082122

    申请日：2016-03-28

    Applicant: International Business Machines Corporation

    Inventor： Khary J. Alexander ,  Michael Billeci ,  Fadi Y. Busaba ,  Mark S. Farrell ,  Christian Jacobi ,  Timothy J. Slegel

    IPC: G06F9/50 ,  G06F9/38

    CPC classification number: G06F9/3861 ,  G06F9/5005

    Abstract: In one embodiment, a computer-implemented method includes requesting, by a first processor thread of a computer processor, access to exception tracking logic. The exception tracking logic is accessible by a plurality of processor threads. The first processor thread receives access to the exception tracking logic. The first processor thread executes a process in slow mode. Based on detecting an exception in slow mode, the first processor thread stores, in the exception tracking logic, exception information about the exception. The exception information is copied from the exception tracking logic to a set of external registers outside the exception tracking logic. The exception tracking logic is released to allow access to the exception tracking logic by other processor threads of the plurality of processor threads.

    Abstract translation: 在一个实施例中，计算机实现的方法包括由计算机处理器的第一处理器线程请求访问异常跟踪逻辑。 异常跟踪逻辑可由多个处理器线程访问。 第一个处理器线程接收到异常跟踪逻辑的访问。 第一个处理器线程以慢速模式执行进程。 基于在慢速模式下检测异常，第一处理器线程在异常跟踪逻辑中存储有关异常的异常信息。 异常信息从异常跟踪逻辑复制到异常跟踪逻辑之外的一组外部寄存器。 异常跟踪逻辑被释放以允许通过多个处理器线程的其他处理器线程访问异常跟踪逻辑。

    Scheme for verifying the effects of program optimizations
    68.
    发明授权
    Scheme for verifying the effects of program optimizations 有权
    验证程序优化效果的方案

    公开(公告)号：US09495138B1

    公开(公告)日：2016-11-15

    申请号：US14987377

    申请日：2016-01-04

    Applicant: International Business Machines Corporation

    Inventor： Giles R. Frazier ,  Michael Karl Gschwind ,  Christian Jacobi ,  Anthony Saporito ,  Chung-Lung K. Shum

    IPC: G06F9/45

    CPC classification number: G06F8/443 ,  G06F8/4441 ,  G06F9/44589

    Abstract: Techniques relate for verifying an effect of software program optimization. A determination is made whether a fingerprint is present in a software application that is currently executing on a processor of a computer system, where the fingerprint includes a representation of a sequence of behavior that occurs on the processor while the software application is executing. The fingerprint corresponds to an optimization made to the software application. In response to determining that the fingerprint is not present in the software application currently executing on the processor, it is determined that the optimization to the software application did not have an intended effect. In response to determining that the fingerprint is present in the software application executing on the processor, it is recognized that the optimization to the software application has the intended effect.

    Abstract translation: 技术涉及验证软件程序优化的效果。 确定当前在计算机系统的处理器上执行的软件应用程序中是否存在指纹，其中指纹包括在软件应用程序执行时在处理器上发生的行为序列的表示。 指纹对应于对软件应用进行的优化。 响应于确定当前在处理器上执行的软件应用程序中不存在指纹，确定对软件应用程序的优化没有预期的效果。 响应于确定在处理器上执行的软件应用中存在指纹，认识到对软件应用的优化具有预期的效果。

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