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    Rapid melt growth photodetector
    61.
    发明授权
    Rapid melt growth photodetector 有权

    公开(公告)号：US10103280B1

    公开(公告)日：2018-10-16

    申请号：US15486810

    申请日：2017-04-13

    Applicant: International Business Machines Corporation

    Inventor： John J. Ellis-Monaghan ,  Edward W. Kiewra ,  Jason S. Orcutt

    IPC: H01L31/02 ,  H01L31/0232 ,  G02B6/42 ,  G02B6/12

    Abstract: Photodetector including: a waveguide of a waveguide material extending over a substrate; an insulating layer formed over the waveguide and having an opening exposing the waveguide; a photodetector layer formed over the insulating layer and into the opening so as to make contact with the waveguide, the photodetector layer having a first end at the opening and a second end distal from the opening, the photodetector layer being a gradient material of the waveguide material and germanium wherein a waveguide material portion of the gradient material varies from a maximum at the first end to a minimum at the second end and wherein a germanium portion of the gradient material varies from a minimum at the first end to a maximum at the second end; a photodetector region at the second end; and a photodetector layer extension extending at an angle from the photodetector layer at the second end.

    MULTILEVEL WAVEGUIDE STRUCTURE
    65.
    发明申请
    MULTILEVEL WAVEGUIDE STRUCTURE 有权
    多波形结构

    公开(公告)号：US20160377806A1

    公开(公告)日：2016-12-29

    申请号：US14749907

    申请日：2015-06-25

    Applicant: International Business Machines Corporation

    Inventor： John J. Ellis-Monaghan ,  Brendan S. Harris ,  Vibhor Jain ,  Yves T. Ngu ,  Sebastian T. Ventrone

    IPC: G02B6/125 ,  G02B6/122 ,  G02B6/13 ,  G02B6/12

    CPC classification number: G02B6/125 ,  G02B6/12002 ,  G02B6/1228 ,  G02B6/13 ,  G02B6/30 ,  G02B2006/12061 ,  G02B2006/12147 ,  G02B2006/12195

    Abstract: Integrated optical structures include a first wafer layer, a first insulator layer directly connected to the top of the first wafer layer, a second wafer layer directly connected to the top of the first insulator layer, a second insulator layer directly connected to the top of the second wafer layer, and a third wafer layer directly connected to the top of the second insulator layer. Such structures include: a first optical waveguide positioned within the second wafer layer; an optical coupler positioned within the second wafer layer, the second insulator layer, and the third wafer layer; and a second optical waveguide positioned within the third wafer layer. The optical coupler transmits an optical beam from the first optical waveguide to the second optical waveguide through the second insulator layer.

    Abstract translation: 集成光学结构包括第一晶片层，直接连接到第一晶片层顶部的第一绝缘体层，直接连接到第一绝缘体层顶部的第二晶体层，直接连接到第一晶体层顶部的第二绝缘体层 第二晶片层和直接连接到第二绝缘体层的顶部的第三晶片层。 这种结构包括：位于第二晶片层内的第一光波导; 位于所述第二晶片层内的光耦合器，所述第二绝缘体层和所述第三晶片层; 以及位于第三晶片层内的第二光波导。 光耦合器通过第二绝缘体层将光束从第一光波导传输到第二光波导。

    Silicon photonics alignment tolerant vertical grating couplers
    66.
    发明授权
    Silicon photonics alignment tolerant vertical grating couplers 有权
    硅光子对准容限垂直光栅耦合器

    公开(公告)号：US09274283B1

    公开(公告)日：2016-03-01

    申请号：US14501720

    申请日：2014-09-30

    Applicant: International Business Machines Corporation

    Inventor： John J. Ellis-Monaghan ,  William M. J. Green ,  Jens Hofrichter ,  Marwan H. Khater ,  Jessie C. Rosenberg ,  Steven M. Shank

    IPC: G02B6/34 ,  G02B6/132 ,  G02B6/30 ,  G02B6/12

    CPC classification number: G02B6/34 ,  G02B6/12002 ,  G02B6/132 ,  G02B6/30 ,  G02B2006/12107

    Abstract: Disclosed are optoelectronic integrated circuit structures that incorporate a first optical waveguide, having a semiconductor core, indirectly coupled to a grating coupler through a second optical waveguide, having a dielectric core, in order provide a relatively large alignment tolerance. The dielectric core can comprise multiple dielectric layers above one end of the semiconductor core and extending laterally over an isolation region adjacent to that end. The grating coupler can include dielectric fins above the isolation region. Alternatively, the grating coupler can include semiconductor fins within the isolation region. Also disclosed herein are methods of forming such optoelectronic integrated circuit structures that can be readily integrated with complementary metal oxide semiconductor (CMOS) device processing and germanium photodetector processing.

    Abstract translation: 公开了光电集成电路结构，其结合有第一光波导，其具有通过第二光波导间接耦合到光栅耦合器的半导体芯，其具有介电芯，以提供相对大的对准公差。 电介质芯可以包括在半导体芯的一端上方的多个电介质层，并且横向延伸在与该端相邻的隔离区上。 光栅耦合器可以包括隔离区上方的介质鳍片。 或者，光栅耦合器可以包括隔离区域内的半导体鳍片。 本文还公开了形成这样的光电子集成电路结构的方法，该结构可以容易地与互补金属氧化物半导体（CMOS）器件处理和锗光电检测器处理集成。

    Use of contacts to create differential stresses on devices
    67.
    发明授权
    Use of contacts to create differential stresses on devices 有权
    使用触点在器件上产生差分应力

    公开(公告)号：US09196528B2

    公开(公告)日：2015-11-24

    申请号：US13798643

    申请日：2013-03-13

    Applicant: International Business Machines Corporation

    Inventor： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin ,  Robert R. Robison

    IPC: H01L21/8238 ,  H01L21/768 ,  H01L27/092

    CPC classification number: H01L21/76879 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L27/092

    Abstract: Disclosed herein are various methods and structures using contacts to create differential stresses on devices in an integrated circuit (IC) chip. An IC chip is disclosed having a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET), a PFET contact to a source/drain region of the PFET and an NFET contact to a source/drain region of the NFET. In a first embodiment, a silicon germanium (SiGe) layer is included only under the PFET contact, between the PFET contact and the source/drain region of the PFET. In a second embodiment, either the PFET contact extends into the source/drain region of the PFET or the NFET contact extends into the source/drain region of the NFET.

    Abstract translation: 这里公开了使用触点在集成电路（IC）芯片中的器件上产生差分应力的各种方法和结构。 公开了具有p型场效应晶体管（PFET）和n型场效应晶体管（NFET）的IC芯片，与PFET的源极/漏极区域的PFET接触以及与源极/漏极区域的NFET接触 的NFET。 在第一实施例中，在PFET接触和PFET的源极/漏极区之间仅包含PFET接触下的硅锗（SiGe）层。 在第二实施例中，PFET触点延伸到PFET的源极/漏极区域中，或者NFET触点延伸到NFET的源极/漏极区域。

    Encapsulated sensors
    68.
    发明授权
    Encapsulated sensors 有权
    封装传感器

    公开(公告)号：US09171971B2

    公开(公告)日：2015-10-27

    申请号：US14068461

    申请日：2013-10-31

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  William J. Murphy ,  Kirk D. Peterson ,  Steven M. Shank

    IPC: H01L31/0203 ,  H01L31/20

    CPC classification number: H01L31/0203 ,  H01L31/1872 ,  H01L31/208 ,  Y02E10/50 ,  Y02P70/521

    Abstract: An encapsulated sensors and methods of manufacture are disclosed herein. The method includes forming an amorphous or polycrystalline material in contact with a layer of seed material. The method further includes forming an expansion space for the amorphous or polycrystalline material. The method further includes forming an encapsulation structure about the amorphous or polycrystalline material. The method further includes crystallizing the amorphous or polycrystalline material by a thermal anneal process such that the amorphous or polycrystalline material expands within the expansion space.

    Abstract translation: 封装的传感器和制造方法在本文中公开。 该方法包括形成与种子材料层接触的无定形或多晶材料。 该方法还包括形成用于非晶或多晶材料的膨胀空间。 该方法还包括形成关于非晶或多晶材料的封装结构。 该方法还包括通过热退火工艺使非晶或多晶材料结晶，使得非晶或多晶材料在膨胀空间内膨胀。

    Fabricating polysilicon MOS devices and passive ESD devices
    70.
    发明授权
    Fabricating polysilicon MOS devices and passive ESD devices 有权
    制造多晶硅MOS器件和无源ESD器件

    公开(公告)号：US08951893B2

    公开(公告)日：2015-02-10

    申请号：US13733243

    申请日：2013-01-03

    Applicant: International Business Machines Corporation

    Inventor： John J. Ellis-Monaghan ,  Michael J. Hauser ,  Zhong-Xiang He ,  Junjun Li ,  Xuefeng Liu ,  Anthony K. Stamper

    IPC: H01L27/04 ,  H01L21/36 ,  H01L21/84 ,  H01L27/12

    CPC classification number: B81C1/00301 ,  B81B7/007 ,  B81B2207/094 ,  B81C1/00246 ,  B81C2203/0714 ,  B81C2203/0742 ,  H01L21/84 ,  H01L27/1203

    Abstract: A semiconductor fabrication is described, wherein a MOS device and a MEMS device is fabricated simultaneously in the BEOL process. A silicon layer is deposited and etched to form a silicon film for a MOS device and a lower silicon sacrificial film for a MEMS device. A conductive layer is deposited atop the silicon layer and etched to form a metal gate and a first upper electrode. A dielectric layer is deposited atop the conductive layer and vias are formed in the dielectric layer. Another conductive layer is deposited atop the dielectric layer and etched to form a second upper electrode and three metal electrodes for the MOS device. Another silicon layer is deposited atop the other conductive layer and etched to form an upper silicon sacrificial film for the MEMS device. The upper and lower silicon sacrificial films are then removed via venting holes.

    Abstract translation: 描述了半导体制造，其中在BEOL工艺中同时制造MOS器件和MEMS器件。 沉积并蚀刻硅层以形成用于MOS器件的硅膜和用于MEMS器件的下硅牺牲膜。 导电层沉积在硅层顶部并被蚀刻以形成金属栅极和第一上电极。 介电层沉积在导电层顶上，并且通孔形成在电介质层中。 另一个导电层沉积在电介质层顶上并被蚀刻以形成用于MOS器件的第二上电极和三个金属电极。 另一硅层沉积在另一导电层的顶上，并被蚀刻以形成用于MEMS器件的上硅牺牲膜。 然后通过排气孔去除上部和下部硅牺牲膜。

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