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    Frequency calibration with real-time resistor trimming
    62.
    发明授权
    Frequency calibration with real-time resistor trimming 有权
    频率校准与实时电阻修剪

    公开(公告)号：US09252794B1

    公开(公告)日：2016-02-02

    申请号：US14484329

    申请日：2014-09-12

    Applicant: International Business Machines Corporation

    Inventor： Kai Di Feng ,  David R. Hanson ,  Chengwen Pei ,  Ping-Chuan Wang

    IPC: H03K3/03 ,  H03L7/24

    CPC classification number: H03K3/0315 ,  H03L7/00

    Abstract: An on-chip frequency calibration apparatus is described. A ring oscillator generates a clock signal. A trimmable resistor is coupled to the ring oscillator. A frequency detector detects the frequency of the clock signal generated from the ring oscillator. The frequency detector includes a frequency divider component that divides the frequency of the clock signal by a predetermined number to derive an output signal having a pulse duration that is equal to at least one period of the clock signal, a capacitor, a capacitor charging current source, and a capacitor charge transistor directs a charging current generated from the capacitor charging current source to the capacitor as a function of the output signal generated from the frequency divider component. A resistor trimming unit trims the trimmable resistor in response to determining that the frequency detected by the frequency detector is less than a target frequency threshold.

    Abstract translation: 描述了片上频率校准装置。 环形振荡器产生时钟信号。 可调节电阻器耦合到环形振荡器。 频率检测器检测从环形振荡器产生的时钟信号的频率。 频率检测器包括分频器部件，其将时钟信号的频率除以预定数量，以导出具有等于时钟信号的至少一个周期的脉冲持续时间的输出信号，电容器，电容器充电电流源 并且电容器充电晶体管将从电容器充电电流源产生的充电电流作为从分频器组件产生的输出信号的电容器引导到电容器。 响应于确定频率检测器检测到的频率小于目标频率阈值，电阻微调单元修整可调整电阻器。

    PHYSICAL UNCLONABLE INTERCONNECT FUNCTION ARRAY
    63.
    发明申请
    PHYSICAL UNCLONABLE INTERCONNECT FUNCTION ARRAY 有权
    物理不可变的互连功能阵列

    公开(公告)号：US20150348899A1

    公开(公告)日：2015-12-03

    申请号：US14825303

    申请日：2015-08-13

    Applicant: International Business Machines Corporation

    Inventor： Kai D. Feng ,  Wai-Kin Li ,  Ping-Chuan Wang ,  Zhijian Yang

    IPC: H01L23/522 ,  H01L23/528

    CPC classification number: H01L23/5222 ,  H01L21/0274 ,  H01L21/3212 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/7684 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H04L9/3278 ,  H04L2209/12 ,  H05K1/0289 ,  Y10T29/49117 ,  Y10T29/49165 ,  H01L2924/00

    Abstract: A method for fabricating an interconnect function array includes forming a first plurality of conductive lines on a substrate, forming an insulator layer over the first plurality of conductive lines and the substrate, removing portions of the insulator layer to define cavities in the insulator layer that expose portions of the substrate and the first plurality of conductive lines, wherein the removal of the portions of the insulator layer results in a substantially random arrangement of cavities exposing portions of the substrate and the first plurality of conductive lines, depositing a conductive material in the cavities, and forming a second plurality of conductive lines on portions of the conductive material in the cavities and the insulator layer.

    Abstract translation: 一种用于制造互连功能阵列的方法包括在衬底上形成第一多条导线，在第一多条导线和衬底之上形成绝缘体层，去除绝缘体层的部分以限定暴露在绝缘体层中的空腔 衬底和第一多个导电线的部分，其中去除绝缘体层的部分导致暴露衬底和第一多个导电线的部分的空腔的基本上随机的排列，在腔中沉积导电材料 并且在所述空腔和所述绝缘体层中的所述导电材料的部分上形成第二多个导电线。

    WAFER THINNING ENDPOINT DETECTION FOR TSV TECHNOLOGY
    65.
    发明申请
    WAFER THINNING ENDPOINT DETECTION FOR TSV TECHNOLOGY 有权
    TSV技术的冷却端点检测

    公开(公告)号：US20150206809A1

    公开(公告)日：2015-07-23

    申请号：US14161738

    申请日：2014-01-23

    Applicant: International Business Machines Corporation

    Inventor： Hanyi Ding ,  Oleg Gluschenkov ,  Ping-Chuan Wang ,  Lin Zhou

    IPC: H01L21/66 ,  H01L21/67 ,  H01L21/683

    CPC classification number: H01L22/26 ,  H01L21/30625 ,  H01L21/76898 ,  H01L22/14

    Abstract: Embodiments of the present invention provide an apparatus and method for wafer thinning endpoint detection. Embodiments of the present invention utilize through silicon via (TSV) structures formed in the wafer. A specially made wafer handle is bonded to the wafer. Conductive slurry is used in the wafer backside thinning process. The wafer handle provides electrical connectivity to an electrical measurement tool, and conductive posts in the wafer handle are proximal to a test structure on the wafer. A plurality of electrically isolated TSVs is monitored via the electrical measurement tool. When the TSVs are exposed on the backside as a result of thinning, the conductive slurry shorts the electrically isolated TSVs, changing the electrical properties of the plurality of TSVs. The change in electrical properties is detected and used to trigger termination of the wafer backside thinning process.

    Abstract translation: 本发明的实施例提供了一种用于晶片薄化端点检测的装置和方法。 本发明的实施例利用在晶片中形成的硅通孔（TSV）结构。 特殊制造的晶圆把手与晶片结合。 导电浆料用于晶片背面变薄处理。 晶片手柄提供与电测量工具的电连接，并且晶片把手中的导电柱靠近晶片上的测试结构。 通过电测量工具监测多个电隔离TSV。 当TSV由于变薄而暴露在背面时，导电浆料使电隔离的TSV短路，改变多个TSV的电性能。 检测电特性的变化并用于触发晶圆背面变薄过程的终止。

    Clock phase shift detector
    66.
    发明授权
    Clock phase shift detector 有权
    时钟相移检测器

    公开(公告)号：US09077319B2

    公开(公告)日：2015-07-07

    申请号：US14156795

    申请日：2014-01-16

    Applicant: International Business Machines Corporation

    Inventor： Kai D. Feng ,  Jong-ru Guo ,  Trushil N. Shah ,  Ping-Chuan Wang ,  Zhijian Yang

    IPC: H03K5/00 ,  H03L7/087

    CPC classification number: H03K5/00 ,  H03L7/087

    Abstract: A clock phase shift detector circuit may include a phase detector that receives a first and a second clock signal, whereby the phase detector generates a phase signal based on a phase difference between the first and the second clock signal. A first integrator is coupled to the phase detector, receives the phase signal, and generates an integrated phase signal. A second integrator receives the first clock signal and generates an integrated first clock signal. A comparator is coupled to the first and the second integrator, whereby the comparator receives the integrated phase signal and the integrated first clock signal. The comparator may then generate a control signal that detects a change between the phase difference of the first and the second clock signal and an optimized phase difference based on an amplitude comparison between the integrated phase signal and the integrated first clock signal.

    Abstract translation: 时钟相移检测器电路可以包括接收第一和第二时钟信号的相位检测器，由此相位检测器基于第一和第二时钟信号之间的相位差产生相位信号。 第一积分器耦合到相位检测器，接收相位信号，并产生积分相位信号。 第二积分器接收第一时钟信号并产生积分的第一时钟信号。 比较器耦合到第一和第二积分器，由此比较器接收积分相位信号和集成的第一时钟信号。 然后，比较器可以产生控制信号，该控制信号基于积分相位信号和集成的第一时钟信号之间的幅度比较来检测第一和第二时钟信号的相位差与优化的相位差之间的变化。

    Interconnect with hybrid metallization
    67.
    发明授权
    Interconnect with hybrid metallization 有权
    与混合金属化相互连接

    公开(公告)号：US09059166B2

    公开(公告)日：2015-06-16

    申请号：US13890560

    申请日：2013-05-09

    Applicant: International Business Machines Corporation

    Inventor： Ronald G. Filippi ,  Erdem Kaltalioglu ,  Ping-Chuan Wang ,  Lijuan Zhang

    IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

    CPC classification number: H01L23/5226 ,  H01L21/76805 ,  H01L21/76834 ,  H01L21/76885 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An electronic interconnect structure having a hybridized metal structure near regions of high operating temperature on an integrated circuit, and methods of making the same. The hybridized metal structure features at least two different metals in a single metallization level. The first metal is in a region of high operating temperature and the second region is in a region of normal operating temperatures. In a preferred embodiment the first metal includes aluminum and is in a first level metallization over an active area of the device while the second metal includes copper. In some embodiments, the first and second metals are not in direct physical contact. In other embodiments the first and second metals physically contact each other. In a preferred embodiment, a top surface of the first metal is not co-planar with a top surface of the second metal, despite being in the same metallization level.

    Abstract translation: 一种在集成电路上具有高工作温度区域附近的杂化金属结构的电子互连结构及其制造方法。 杂化金属结构在单一金属化水平中具有至少两种不同的金属。 第一金属处于高工作温度的区域，第二区域处于正常操作温度的区域。 在优选实施例中，第一金属包括铝，并且在器件的有效区域上处于第一级金属化，而第二金属包括铜。 在一些实施例中，第一和第二金属不是直接的物理接触。 在其他实施例中，第一和第二金属物理地彼此接触。 在优选实施例中，尽管处于相同的金属化水平，第一金属的顶表面与第二金属的顶表面不共面。

    ON-CHIP STRUCTURE FOR SECURITY APPLICATION
    69.
    发明申请
    ON-CHIP STRUCTURE FOR SECURITY APPLICATION 有权
    安全应用的芯片结构

    公开(公告)号：US20150154421A1

    公开(公告)日：2015-06-04

    申请号：US14096345

    申请日：2013-12-04

    Applicant: International Business Machines Corporation

    Inventor： Kai Di Feng ,  Wai-Kin Li ,  Chengwen Pei ,  Ping-Chuan Wang

    IPC: G06F21/71 ,  G06F7/58

    CPC classification number: G06F21/71 ,  G06F7/588 ,  G06F21/73

    Abstract: A set of physical unclonable function (PUF) cells is configured with a set of capacitive devices in an integrated circuit (IC). A subset of PUF cells includes a corresponding subset of capacitive devices that have failed during fabrication. A charging current sufficient to charge an operational capacitive device in a PUF cell is sent to the set of PUF cells. A determination is made whether an output voltage of a PUF cell exceeds a threshold. When the output voltage exceeding the threshold, a logic value of 1 is produced at a position in a bit-string. The determination and the producing is repeated for each PUF cell in the set to output a bit-string, which includes 1s and 0s in random positions. The bit-string is used in a security application as a random stable value owing to a random pattern of 1s and 0s present in the bit-string.

    Abstract translation: 一组物理不可克隆功能（PUF）单元在集成电路（IC）中配置有一组电容性器件。 PUF单元的子集包括在制造期间失败的电容器件的相应子集。 向PUF单元中的操作电容性装置充电的充电电流被发送到PUF单元组。 确定PUF单元的输出电压是否超过阈值。 当输出电压超过阈值时，在位串中的位置产生逻辑值1。 对集合中的每个PUF单元重复确定和产生，以输出位串，其包括随机位置中的1和0。 由于位串中存在1和0的随机模式，因此位串在安全应用程序中用作随机稳定值。

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