公开(公告)号：US07830739B2

公开(公告)日：2010-11-09

申请号：US12457962

申请日：2009-06-26

申请人： Kazuhiko Kajigaya

发明人： Kazuhiko Kajigaya

IPC分类号： G11C7/02

CPC分类号： G11C8/10 ,  G06F12/0893 ,  G06F2212/1016 ,  G06F2212/3042 ,  G11C7/065 ,  G11C7/1039 ,  G11C7/18 ,  G11C8/08 ,  G11C11/4091 ,  G11C11/4093 ,  G11C2207/005 ,  G11C2207/2245

摘要： A semiconductor memory device of the invention comprises unit blocks into which the memory cell array is divided, rows of sense amplifiers arranged at one end and the other end of the plurality of bit lines in the unit block, switch means for switching a connection state between the unit block and the row of sense amplifiers attached to the unit block; and control means for controlling the switch means so as to form a transfer path from the row of sense amplifiers attached to a predetermined the unit block leading to the row of sense amplifiers as a saving destination not attached to the predetermined the unit block. This row of sense amplifiers attached to the predetermined the unit block functions as a cache memory.

摘要翻译： 本发明的半导体存储器件包括存储单元阵列被划分成的单位块，布置在单元块中的多个位线的一端和另一端的读出放大器行，用于切换单元块之间的连接状态的开关装置 单元块和连接到单元块的读出放大器的行; 以及用于控制开关装置的控制装置，以便形成从附接到预定的单位块的读出放大器行的传送路径，该预定的单位块通向作为不附加到预定单位块的保存位置的读出放大器行。 附加到预定单元块的该行读出放大器用作高速缓冲存储器。

公开(公告)号：US07830738B2

公开(公告)日：2010-11-09

申请号：US12116264

申请日：2008-05-07

申请人： Kazuhiko Kajigaya

发明人： Kazuhiko Kajigaya

IPC分类号： G11C7/00

CPC分类号： G11C11/4097 ,  G11C7/02 ,  G11C11/4094 ,  G11C2207/002

摘要： A semiconductor memory device comprises. word lines; global bit lines intersecting with the word lines; local bit lines partitioned into N (N is an integer greater than or equal to two) sections along the global bit lines and aligned with a same pitch as the global bit lines; N memory cell arrays each including memory cells each having cylindrical capacitor structure formed at intersections of the word lines and the local bit lines and being arranged corresponding to the sections of the local bit lines; local sense amplifiers for amplifying a signal read out from a selected memory cell to the local bit line and for outputting the signal to the global bit line; and global sense amplifiers for coupling the signal transmitted from the local sense amplifier corresponding to the selected memory cell through the global bit line to an external data line.

摘要翻译： 半导体存储器件包括。 字线 全局位线与字线相交; 沿着全局位线将局部位线划分成N（N是大于或等于2的整数）部分，并且与全局位线以相同的间距对齐; N个存储单元阵列，每个存储单元阵列包括形成在字线和局部位线的交点处并且对应于局部位线的部分布置的圆柱形电容器结构的存储单元; 本地读出放大器，用于将从所选存储单元读出的信号放大到本地位线，并将该信号输出到全局位线; 以及用于将对应于所选择的存储器单元的本地读出放大器发送的信号通过全局位线耦合到外部数据线的全局读出放大器。

公开(公告)号：US07719877B2

公开(公告)日：2010-05-18

申请号：US12142133

申请日：2008-06-19

申请人： Kazuhiko Kajigaya

发明人： Kazuhiko Kajigaya

IPC分类号： G11C11/24

CPC分类号： G11C11/4085 ,  G11C7/02 ,  G11C7/18 ,  G11C11/4074 ,  G11C11/4097

摘要： To increase the quantity of stored charges of memory cells by a simple configuration to improve the operating margin, and to allow dummy cells to be unnecessary to improve the operating margin of a DRAM without increasing the power consumption and/or the chip area. A voltage of a common plate line is changed from a first voltage to a second voltage lower than the first voltage while a word line is a third voltage which makes the word line a selected state. The voltage of the word line is changed into a fourth voltage which makes the memory cell a non-selected state and is lower than the third voltage and higher than a fifth voltage which makes the word line a non-selected state, and the voltage of the plate line is changed into the first voltage after the voltage of the word line has been changed into the fourth voltage.

摘要翻译： 为了通过简单的配置增加存储器单元的存储电荷量以提高操作裕度，并且允许虚拟单元不需要增加DRAM的操作余量，而不增加功耗和/或芯片面积。 公共板线的电压从第一电压变为低于第一电压的第二电压，而字线是使字线成为选定状态的第三电压。 字线的电压变为使存储单元为非选择状态且低于第三电压且高于使字线为非选择状态的第五电压的第四电压， 在字线的电压已经变为第四电压之后，板线被改变为第一电压。

公开(公告)号：US07688670B2

公开(公告)日：2010-03-30

申请号：US12165681

申请日：2008-07-01

申请人： Masashi Horiguchi ,  Masayuki Nakamura ,  Sadayuki Ohkuma ,  Kazuhiko Kajigaya ,  Yoshinobu Nakagome

发明人： Masashi Horiguchi ,  Masayuki Nakamura ,  Sadayuki Ohkuma ,  Kazuhiko Kajigaya ,  Yoshinobu Nakagome

IPC分类号： G11C7/00

CPC分类号： G11C5/063 ,  G11C5/14 ,  G11C5/147 ,  G11C7/1072 ,  G11C8/12 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40618 ,  G11C11/4074 ,  G11C11/4076 ,  G11C2207/2227 ,  G11C2211/4067 ,  G11C2211/4068

摘要： A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both receive externally supplied voltages and output internal supply voltages. The first power supply circuit is not in operation when a semiconductor device of the synchronous DRAM is in a power down mode. However, the second power supply circuit is continuously in operation during the power down mode. In another arrangement, the operation of a voltage limiter circuit is controlled based on whether or not the DRAM is in a power down mode.

摘要翻译： 提供了一种同步DRAM，其包括基于DRAM是否处于掉电模式的电源电路的操作的布置。 在一个实施例中，提供了第一电源电路和第二电源电路，其接收外部提供的电压并输出内部电源电压。 当同步DRAM的半导体器件处于掉电模式时，第一电源电路不工作。 然而，第二电源电路在掉电模式期间连续运行。 在另一种布置中，基于DRAM是否处于断电模式来控制限压器电路的操作。

公开(公告)号：US07573767B2

公开(公告)日：2009-08-11

申请号：US11882827

申请日：2007-08-06

申请人： Kazuhiko Kajigaya

发明人： Kazuhiko Kajigaya

IPC分类号： G11C7/02

CPC分类号： G11C8/10 ,  G06F12/0893 ,  G06F2212/1016 ,  G06F2212/3042 ,  G11C7/065 ,  G11C7/1039 ,  G11C7/18 ,  G11C8/08 ,  G11C11/4091 ,  G11C11/4093 ,  G11C2207/005 ,  G11C2207/2245

摘要： A semiconductor memory device of the invention comprises unit blocks into which the memory cell array is divided, rows of sense amplifiers arranged at one end and the other end of the plurality of bit lines in the unit block, switch means for switching a connection state between the unit block and the row of sense amplifiers attached to the unit block; and control means for controlling the switch means so as to form a transfer path from the row of sense amplifiers attached to a predetermined the unit block leading to the row of sense amplifiers as a saving destination not attached to the predetermined the unit block. This row of sense amplifiers attached to the predetermined the unit block functions as a cache memory.

公开(公告)号：US20090122602A1

公开(公告)日：2009-05-14

申请号：US12352668

申请日：2009-01-13

申请人： RIICHIRO TAKEMURA ,  Takeshi Sakata ,  Norikatsu Takaura ,  Kazuhiko Kajigaya

发明人： RIICHIRO TAKEMURA ,  Takeshi Sakata ,  Norikatsu Takaura ,  Kazuhiko Kajigaya

IPC分类号： G11C11/00 ,  G11C8/08 ,  G11C7/00

CPC分类号： G11C13/0069 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1096 ,  G11C8/08 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/004 ,  G11C2213/79

摘要： There is achieved a high-integrated and high-speed nonvolatile memory which can stabilize an operation of a phase-change memory for a short operation cycle time. A latch is provided in a write driver. A change to a high-resistance state of a phase-change element is performed per column cycle by a write-enable signal, and a change to a low-resistance state thereof is performed after a pre-charge command is inputted and concurrently with deactivation of a pre-charge signal. Thereby, a write time to a memory cell in which phase-change resistance is changed to a low-resistance state, and a period from a write operation for changing the phase-change resistance to a high-resistance state to a read operation to the above memory cell can be lengthened without extending the column cycle time, so that the stable write operation is achieved.

摘要翻译： 实现了高集成度和高​​速度的非易失性存储器，其可以在短的操作周期时间内稳定相变存储器的操作。 在写入驱动器中提供锁存器。 通过写使能信号，每列循环执行相变元件的高电阻状态的改变，并且在预充电命令被输入之后执行到其低电阻状态的改变，并且同时具有去激活 的预充电信号。 由此，对相变电阻变为低电阻状态的存储单元的写入时间，以及从相变电阻改变为高电阻状态到读操作的写操作的周期 可以延长上述存储单元，而不延长列周期时间，从而实现稳定的写操作。

公开(公告)号：US20090100220A1

公开(公告)日：2009-04-16

申请号：US12285745

申请日：2008-10-14

申请人： Kazuhiko Kajigaya

发明人： Kazuhiko Kajigaya

IPC分类号： G06F12/00

CPC分类号： G11C7/22 ,  G11C2207/2209 ,  G11C2207/2245

摘要： A memory system includes a memory cell array for storing data; and a register unit including one or more registers for storing system information. In the memory system, when a simultaneous access to the memory cell array and the register unit is requested, write data for the memory cell array is inputted after write data for the register unit is inputted, respectively through a common data input bus in a write operation, and read data from the memory cell array is outputted after read data from the register unit is outputted, respectively through a common data output bus in a read operation.

摘要翻译： 存储器系统包括用于存储数据的存储单元阵列; 以及包括用于存储系统信息的一个或多个寄存器的寄存器单元。 在存储器系统中，当请求同时访问存储单元阵列和寄存器单元时，分别通过写入的公共数据输入总线输入用于寄存器单元的写入数据之后的存储单元阵列的写入数据 在读取操作中，通过公共数据输出总线分别输出来自寄存器单元的读取数据之后，输出来自存储单元阵列的操作和读取数据。

公开(公告)号：US07511347B2

公开(公告)日：2009-03-31

申请号：US11281743

申请日：2005-11-18

申请人： Kazuhiko Kajigaya ,  Kanji Otsuka

发明人： Kazuhiko Kajigaya ,  Kanji Otsuka

IPC分类号： H01L27/092

CPC分类号： G11C7/1051 ,  G11C7/1057 ,  H01L27/092

摘要： A semiconductor integrated circuit comprising: a pair of MOS transistors which are formed in a same well on a semiconductor substrate and arranged adjacent to each other with a distance such that charge exchange between capacitances of respective drain diffusion layers is possible; and a wiring structure which is formed to apply differential signals to respective gates of the pair of MOS transistors and to apply a common potential to respective sources of the pair of MOS transistors.

摘要翻译： 一种半导体集成电路，包括：一对MOS晶体管，其形成在半导体衬底上的相同阱中并且彼此相邻布置，使得可以使各个漏极扩散层的电容之间的电荷交换成为可能; 以及布线结构，其被形成为将差分信号施加到所述一对MOS晶体管的各个栅极，并向所述一对MOS晶体管的各个源施加公共电位。

公开(公告)号：US20080280415A1

公开(公告)日：2008-11-13

申请号：US12149439

申请日：2008-05-01

申请人： Kazuhiko Kajigaya

发明人： Kazuhiko Kajigaya

IPC分类号： H01L21/20

CPC分类号： H01L27/101 ,  G11C11/005 ,  G11C13/00 ,  G11C13/0007 ,  G11C13/0033 ,  G11C2213/31 ,  G11C2213/32 ,  H01L27/2436 ,  H01L27/2472 ,  H01L45/085 ,  H01L45/1266 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1675

摘要： A method of manufacturing a semiconductor memory device of the present invention consists of a step of forming a selection transistor and a separate selection transistor and a step of forming a variable resistance element and a capacitance element, characterized by forming the variable resistance element by sequentially laminating a first electrode that is connected to the selection transistor, a variable resistance layer, and a second electrode; forming the capacitance element by sequentially laminating a third electrode that is connected to the separate selection transistor, a dielectric layer, and a fourth electrode; forming the dielectric layer and the variable resistance layer with a mutually identical material; forming either one of the first electrode or the second electrode with the same material as the third electrode and the fourth electrode; and forming the other one of the first electrode or the second electrode with a different material than the third electrode and the fourth electrode.

摘要翻译： 本发明的半导体存储器件的制造方法由形成选择晶体管和单独的选择晶体管的步骤和形成可变电阻元件和电容元件的步骤构成，其特征在于，通过依次层叠形成可变电阻元件 连接到选择晶体管的第一电极，可变电阻层和第二电极; 通过依次层叠连接到分离的选择晶体管的第三电极，电介质层和第四电极来形成电容元件; 用相互相同的材料形成介电层和可变电阻层; 用与第三电极和第四电极相同的材料形成第一电极或第二电极中的任一个; 以及用与第三电极和第四电极不同的材料形成第一电极或第二电极中的另一个。

公开(公告)号：US20080276049A1

公开(公告)日：2008-11-06

申请号：US12149243

申请日：2008-04-29

申请人： Kazuhiko Kajigaya

发明人： Kazuhiko Kajigaya

IPC分类号： G06F12/00

CPC分类号： G06F13/4243 ,  G06F13/1605

摘要： In order to provide a semiconductor memory apparatus which can flexibly change the priority of reading requests when the reading request is issued and which do not exclusively use the memory bus, a semiconductor memory apparatus includes: a main memory which stores data at an address while maintaining a corresponding relationship between the data and the address; a read request input portion receiving a read request which maintains a corresponding relationship between address information that is referred to when reading the data and priority information that indicates priority for reading the data; a read data storing portion which stores the data and priority while maintaining a corresponding relationship thereof; a data reading portion reads the data corresponding to address information which is input by the read request input portion from the main memory; a read data registration portion storing both the priority information input by the read request input and the data read by the data reading portion to the read data storing portion while maintaining a corresponding relationship between the priority information and the data read; and a priority operation control portion which chooses and outputs the data with a highest priority among the priority information and the data that are stored in the read data storing portion while maintaining a corresponding relationship between the priority information and the data.

摘要翻译： 为了提供一种半导体存储装置，其可以在发出读取请求时灵活地改变读取请求的优先级，并且不排他地使用存储器总线，半导体存储装置包括：主存储器，其在维持地址的同时存储数据 数据和地址之间的对应关系; 接收读取请求的读取请求输入部分，其保持在读取数据时参考的地址信息与指示用于读取数据的优先级的优先级信息之间的对应关系; 读取数据存储部分，其保持数据和优先级，同时保持其对应的关系; 数据读取部分从主存储器读取与读取请求输入部分输入的地址信息对应的数据; 读取数据登记部分，同时保持优先级信息和数据读取之间的对应关系，将由读取请求输入输入的优先级信息和由数据读取部分读取的数据存储到读取数据存储部分; 以及优先操作控制部分，在保持优先级信息和数据之间的对应关系的同时，在优先级信息和存储在读取数据存储部分中的数据之间选择并输出具有最高优先级的数据。