公开(公告)号：US06727578B1

公开(公告)日：2004-04-27

申请号：US09392276

申请日：1999-09-09

申请人： David B. Scott ,  Heng-Chih Lin

发明人： David B. Scott ,  Heng-Chih Lin

IPC分类号： H01L2352

CPC分类号： H01L27/0921 ,  H01L27/0203 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device (200) having a substrate routed power supply voltage is disclosed. The semiconductor device (200) includes a relatively highly doped substrate (302) and an epitaxial layer (304) formed over the substrate (302). In one embodiment (200), a surrounding conductive structure (202) is formed on the peripheral edges of the semiconductor device (200) die. The surrounding conductive structure (202) is coupled to the substrate (302). In another embodiment, the back side of the die (404) is coupled to the conductive portion (402) of an integrated circuit package. The conductive portion (402) is coupled to a power supply voltage. In another embodiment (700), the surrounding conductive structure (702) is coupled to a power supply voltage by one or more bond pads (710) formed on, or coupled to, the surrounding conductive structure (702).

摘要翻译： 公开了具有基板路由电源电压的半导体器件（200）。 半导体器件（200）包括相对高掺杂的衬底（302）和形成在衬底（302）上的外延层（304）。 在一个实施例（200）中，在半导体器件（200）管芯的周边边缘上形成周围的导电结构（202）。 周围的导电结构（202）耦合到衬底（302）。 在另一个实施例中，管芯（404）的背面耦合到集成电路封装的导电部分（402）。 导电部分（402）耦合到电源电压。 在另一实施例（700）中，周围的导电结构（702）通过一个或多个在周围的导电结构（702）上形成或耦合到其上的接合焊盘（710）耦合到电源电压。

公开(公告)号：US06278297B1

公开(公告)日：2001-08-21

申请号：US09395592

申请日：1999-09-14

申请人： Stewart M. DeSoto ,  David B. Scott

发明人： Stewart M. DeSoto ,  David B. Scott

IPC分类号： G11C800

CPC分类号： G11C8/08

摘要： A circuit is designed with a decode circuit (313-315) having a first output terminal (319). The decode circuit is coupled to receive an address signal (81, 82, 85) having a first voltage range for producing a first output signal having one of a first and second logic levels. An output circuit (307, 309) is coupled to receive the first output signal and a power supply signal. The output circuit produces a second output signal having a second voltage range. A first latch transistor (301) is coupled to receive the second output signal. The first latch transistor is arranged to couple the first output terminal to a voltage terminal (209) in response to one of a first and second logic state of the second output signal. A second latch transistor (317) is coupled to receive the second output signal. The second latch transistor is arranged to couple the first output terminal to a reference terminal (318) in response to another of the first and second logic state of the second output signal.

公开(公告)号：US6141259A

公开(公告)日：2000-10-31

申请号：US252409

申请日：1999-02-18

申请人： David B. Scott ,  Donald J. Coleman, deceased

发明人： David B. Scott ,  Donald J. Coleman, deceased

IPC分类号： G11C7/12 ,  G11C11/4094 ,  H01L27/108 ,  G11C7/00

CPC分类号： G11C11/4094 ,  G11C7/12 ,  H01L27/10897

摘要： A random access memory (RAM) having a bipolar reduction in array operating voltage is disclosed. In a preferred embodiment, a clamping transfer gate circuit (414) couple pairs of bit lines (BL and /BL) to pairs of sense nodes (410 and 412). The clamping transfer gate circuit (414) includes an n-channel MOS transistor (N401 and N402) in series with a p-channel MOS transistor (P401 and P402) coupling a bit line (BL or /BL) to a sense node (410 or 412). The gates of the n-channel transistors (N401 and N402) are driven by the high power supply voltage (VDD), and the gates of the p-channel transistors (P401 and P402) are driven by the low power supply voltage (VSS). A sense amplifier circuit (418) drives the sense node pair (410 and 412) to opposite power supply voltages (VDD and VSS). The n-channel transistors (N401 and N402) in the clamping transfer gate circuit (414) clamp the voltage on the bit lines (BL and /BL) to a maximum level of VDD-Vtn, where Vtn is the n-channel transistor threshold voltage. The p-channel transistors (P401 and P402) in the clamping transfer gate circuit (414) clamp the voltage on the bit lines (BL and /BL) to a minimum level of VSS+Vtp, where Vtp is the p-channel transistor threshold voltage. For dynamic RAM applications, memory cells having a higher charge storage capability are disclosed to compensate for the lower array voltages used during refresh operations.

摘要翻译： 公开了具有阵列工作电压双极性降低的随机存取存储器（RAM）。 在优选实施例中，钳位传输门电路（414）将成对的位线（BL和/ BL）耦合到感测节点对（410和412）。 钳位传输门电路414包括与将位线（BL或/ BL）耦合到感测节点（410）的p沟道MOS晶体管（P401和P402）串联的n沟道MOS晶体管（N401和N402） 或412）。 n沟道晶体管（N401和N402）的栅极由高电源电压（VDD）驱动，p沟道晶体管（P401和P402）的栅极由低电源电压（VSS）驱动， 。 感测放大器电路（418）将感测节点对（410和412）驱动到相反的电源电压（VDD和VSS）。 钳位传输门电路（414）中的n沟道晶体管（N401和N402）将位线（BL和/ BL）上的电压钳位到VDD-Vtn的最大电平，其中Vtn是n沟道晶体管阈值 电压。 钳位传输门电路（414）中的p沟道晶体管（P401和P402）将位线（BL和/ BL）上的电压钳位到VSS + Vtp的最小电平，其中Vtp是p沟道晶体管阈值 电压。 对于动态RAM应用，公开了具有较高电荷存储能力的存储器单元以补偿刷新操作期间使用的较低阵列电压。

公开(公告)号：US5552724A

公开(公告)日：1996-09-03

申请号：US122273

申请日：1993-09-17

申请人： David B. Scott

发明人： David B. Scott

IPC分类号： H03K19/00 ,  H03K19/086

CPC分类号： H03K19/001 ,  H03K19/086

摘要： Local reference voltage sub-circuits for ECL circuits are provided. The sub-circuits operate by a principal based on gating a current mirror. The sub-circuits described are superior to conventional approaches because less current is required during switching, better transfer characteristics are obtained and there exists, in some cases, less susceptibility to latch-up in comparison with conventional approaches.

摘要翻译： 提供ECL电路的本地参考电压子电路。 子电路由主体基于门电流镜来操作。 所描述的子电路优于常规方法，因为在切换期间需要更少的电流，获得更好的传输特性，并且与常规方法相比，在一些情况下存在较少的闩锁敏感性。

公开(公告)号：US5424660A

公开(公告)日：1995-06-13

申请号：US76040

申请日：1993-06-15

申请人： David B. Scott ,  Harold D. Goodpaster

发明人： David B. Scott ,  Harold D. Goodpaster

IPC分类号： H03K19/00 ,  H03K19/086 ,  H03K19/20

CPC分类号： H03K19/001 ,  H03K19/086

摘要： A differential emitter coupled logic circuit having an output and a compliment of the output, the circuit comprising: a first emitter coupled transistor pair (Q17 and Q18); a second emitter coupled transistor pair (Q19 and Q20); a third emitter coupled transistor pair (Q25 and Q26); a fourth emitter coupled transistor pair (Q33 and Q34); a filch emitter coupled transistor pair (Q37 and Q38); and a sixth emitter coupled transistor pair (Q35 and Q36).

摘要翻译： 一种具有输出和输出的补偿的差分发射极耦合逻辑电路，该电路包括：第一发射极耦合晶体管对（Q17和Q18）; 第二发射极耦合晶体管对（Q19和Q20）; 第三发射极耦合晶体管对（Q25和Q26）; 第四发射极耦合晶体管对（Q33和Q34）; fil射发射极耦合晶体管对（Q37和Q38）; 和第六发射极耦合晶体管对（Q35和Q36）。

公开(公告)号：US5104817A

公开(公告)日：1992-04-14

申请号：US496486

申请日：1990-03-20

申请人： David B. Scott

发明人： David B. Scott

IPC分类号： H01L21/761 ,  H01L21/8248 ,  H01L21/8249

CPC分类号： H01L21/8249 ,  H01L21/761 ,  H01L21/8248 ,  Y10S148/009

摘要： The described embodiments of the present invention provide a bipolar transistor using an integrated field effect load device with one end of the load device integrally formed with the base of the transistor. The gate of the load device is connected to the emitter of the transistor. This structure is particularly advantageous in bipolar-complementary metal oxide semiconductor (BiCMOS) integrated circuitry. The unconnected end of the load device may be connected to the emitter using standard metal interconnection techniques or local interconnection techniques. In an additional embodiment of the invention, the end of the load device not connected to the base may be left unisolated to the substrate and thus connected to ground. It often occurs that the emitter of the bipolar transistor will be connected to ground and thus an automatic connection of the load device between the base and the emitter can be realized. In addition, by removing the isolation, the integrated circuit area required for the isolation may be saved.

摘要翻译： 本发明的所述实施例提供了一种使用集成的场效应负载装置的双极晶体管，该负载装置的一端与晶体管的基极一体形成。 负载器件的栅极连接到晶体管的发射极。 这种结构在双极互补金属氧化物半导体（BiCMOS）集成电路中是特别有利的。 负载设备的未连接端可以使用标准金属互连技术或本地互连技术连接到发射器。 在本发明的另外的实施例中，未连接到基座的负载装置的端部可以被单独地分离到衬底并因此连接到地面。 通常会发生双极晶体管的发射极连接到地，从而可以实现基极和发射极之间的负载装置的自动连接。 此外，通过去除隔离，可以节省隔离所需的集成电路面积。

公开(公告)号：US5102811A

公开(公告)日：1992-04-07

申请号：US614066

申请日：1990-11-13

申请人： David B. Scott

发明人： David B. Scott

IPC分类号： H01L21/331 ,  H01L21/8249 ,  H01L29/10

CPC分类号： H01L29/66272 ,  H01L21/8249 ,  H01L29/1004

摘要： The described embodiments of the present invention show a high voltage bipolar transistor integrated into a bipolar complementary metal oxide semiconductor integrated circuit. The high voltage transistor is fabricated using the available processing steps for fabricating other components in more standard BiCMOS processes. The collector of the transistor is formed using a buried N type region in a P substrate. A P well, rather than the conventional N well is formed above the buried N layer. The collector contact to the buried N layer is fabricated so as to surround the P well to provide a separate base region. A highly doped P type base region is formed with a P+ contact to this region. An N+ emitter is formed by out diffusion from a heavily doped polycrystalline silicon layer formed in contact with the base region. By providing the lightly doped P well as an interface between the collector and the base, the breakdown voltage of the collector/base junction is substantially raised and thus the breakdown voltage from the collector to the emitter is also raised. A transistor thus fabricated is appropriate for high voltage applications.

摘要翻译： 本发明的所述实施例示出了集成到双极互补金属氧化物半导体集成电路中的高电压双极晶体管。 使用可用的处理步骤制造高压晶体管，用于在更标准的BiCMOS工艺中制造其他部件。 晶体管的集电极使用P基板中的掩埋N型区域形成。 在掩埋N层上方形成P阱，而不是常规N阱。 与掩埋N层的集电极接触被制造成围绕P阱以提供单独的基极区域。 高掺杂P型基区形成与该区域的P +接触。 通过从与基极区域接触形成的重掺杂多晶硅层的扩散形成N +发射极。 通过提供轻掺杂P阱作为集电极和基极之间的界面，集电极/基极结的击穿电压基本上升高，从而集电极到发射极的击穿电压也升高。 如此制造的晶体管适用于高电压应用。

公开(公告)号：US4420344A

公开(公告)日：1983-12-13

申请号：US311713

申请日：1981-10-15

申请人： Roderick D. Davies ,  David B. Scott

发明人： Roderick D. Davies ,  David B. Scott

IPC分类号： H01L21/033 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/263 ,  H01L21/26

CPC分类号： H01L21/823814 ,  H01L21/033 ,  H01L27/0928

摘要： CMOS source/drain regions of both conductivity types are formed using only a single masking step. One dopant is applied to both types of source/drain regions, and a second dopant is applied at a much higher dose and energy to only one type of source/drain region. Preferably, boron and arsenic are used as the dopants in silicon, since the cooperative diffusion effect causes the boron in the counterdoped source/drain regions to be entirely contained within the arsenic diffusion.To avoid the erratic etching characteristics of heavily-doped polysilicon under chloro-etch, the patterned photoresist used to pattern the gates and gate-level interconnects is left in place during the P+ source/drain implant. Thus, moderately doped N-type polysilicon may be used, since it is not exposed to compensation by the P+ implant. Since no P+ source/drain mask is required, no double-level photoresist structure is created, and there is consequently no obstacle to reworks. In addition, positive resists may be used in practicing the present invention.

摘要翻译： 仅使用单个掩蔽步骤形成两种导电类型的CMOS源极/漏极区域。 一种掺杂剂被施加到两种类型的源极/漏极区域，并且第二掺杂剂以更高的剂量和能量被施加到仅一种类型的源极/漏极区域。 优选地，硼和砷用作硅中的掺杂剂，因为协同扩散效应导致反掺杂源/漏区中的硼完全包含在砷扩散内。 为了避免在氯蚀刻下重掺杂多晶硅的不规则蚀刻特性，在P +源极/漏极注入期间，用于图案栅极和栅极级互连的图案化的光致抗蚀剂保留在适当的位置。 因此，可以使用中等掺杂的N型多晶硅，因为它不被P +植入物暴露于补偿。 由于不需要P +源极/漏极掩模，因此不会产生双层光刻胶结构，因此无需重新制作。 此外，在实施本发明时可以使用正性抗蚀剂。

公开(公告)号：US4219915A

公开(公告)日：1980-09-02

申请号：US24684

申请日：1979-03-28

申请人： David B. Scott

发明人： David B. Scott

IPC分类号： B23D71/04 ,  B23D73/04 ,  B23D71/00 ,  B21K21/00

CPC分类号： B23D71/04 ,  B23D73/04 ,  Y10T407/18

摘要： An elongate substantially rectangular abrading tool blade, which can be used either for smoothing or for heavy stock removal, is formed of sheet metal and has a multiplicity of ground and hardened cutting teeth distributed over a cutting face of the blade and a multiplicity of associated through-the-blade apertures. The cutting teeth and associated apertures extend in several parallel rows across the blade at an angle other than perpendicular to the longitudinal axis of the blade, with several cutting teeth and associated apertures in each row, all the said cutting teeth facing the same way, namely, perpendicular to the said rows. Each said aperture is directly in front of and adjacent its associated cutting tooth relative to the direction in which the teeth face. Two longitudinal side edge portions of the blade are bent back through an acute angle relative to the cutting face from a longitudinal, substantially flat, middle portion of the blade. The rows of cutting teeth and apertures extend across the full width of the middle portion of the blade and at least to the boundaries of said middle portion with the side edge portions, terminating short of both outside edges of the blade. One of said longitudinal side edge portions comprises edge teeth, which are not ground. The other one of said longitudinal side edge portions is smooth, devoid of edge teeth. The method of making the blade involves the bending back of said longitudinal side edge portions prior to hardening by heat of the blade. The bending back of said longitudinal side edge portions is effected by means of a pair of dies caused to close together and also at the same time to cut the blade from coil.

摘要翻译： 可用于平滑或用于重型材料去除的细长的基本上矩形的研磨工具刀片由金属板形成并且具有分布在刀片的切割面上的多个磨削和硬化的切割齿，并且具有多个相关联的通过 刀片孔。 切割齿和相关的孔以几个平行的排列延伸穿过叶片，其角度不是垂直于叶片的纵向轴线，在每排中具有多个切割齿和相关的孔，所有的切割齿都以相同的方式面对，即 垂直于所述行。 每个所述孔径相对于齿面方向直接位于其相关联的切割齿的前面和之后。 叶片的两个纵向侧边缘部分从叶片的纵向，基本平坦的中间部分相对于切割面向后弯曲成锐角。 切割齿和孔的排延伸穿过叶片的中间部分的整个宽度，并且至少延伸到具有侧边缘部分的所述中间部分的边界，终止于叶片的两个外边缘。 所述纵向侧边缘部分中的一个包括不被磨削的边缘齿。 所述纵向侧边缘部分中的另一个是光滑的，没有边缘齿。 制造刀片的方法涉及在通过刀片的热硬化之前所述纵向侧边缘部分的弯曲。 所述纵向侧边缘部分的弯曲背部通过一对模具实现，以使其彼此靠近并同时从线圈切割刀片。