公开(公告)号：US06525363B1

公开(公告)日：2003-02-25

申请号：US09677433

申请日：2000-10-02

申请人： Josef Willer ,  Bernhard Sell ,  Dirk Schumann

发明人： Josef Willer ,  Bernhard Sell ,  Dirk Schumann

IPC分类号： H01L27108

CPC分类号： H01L28/84 ,  H01L27/10852 ,  H01L27/10876 ,  H01L27/10885 ,  H01L28/86 ,  H01L28/90

摘要： A first capacitor electrode of the capacitor, which is arranged on a surface of a substrate (1), has a lower part (T) and a lateral part (S) arranged thereon. At least a first lateral area of the lateral part (S) is undulatory in such a way that it has bulges and indentations alternately which are formed along lines each running in a plane parallel to the surface of the substrate (1). The lateral part (T) can be produced by depositing conductive material in a depression (V) which is produced in a layer sequence whose layers are composed alternately of a first material and a second material and in which the first material is subjected to wet etching selectively with respect to the second material down to a first depth. The first capacitor electrode is provided with a capacitor dielectric (KD). A second capacitor electrode (P) adjoins the capacitor dielectric (KD).

摘要翻译： 设置在基板（1）的表面上的电容器的第一电容电极具有布置在其上的下部（T）和侧部（S）。 横向部分（S）的至少第一横向区域以这样的方式波动，使得其具有沿着平行于基底（1）的表面的平面中的每条线条沿着线形成的凸起和凹陷。 横向部分（T）可以通过将导电材料沉积在层中产生的凹陷（V）中来制造，层的顺序是层，其层由第一材料和第二材料交替组成，并且其中第一材料经受湿蚀刻 相对于第二材料选择性地到达第一深度。 第一电容器电极设置有电容器电介质（KD）。 第二电容器电极（P）与电容器电介质（KD）相邻。

公开(公告)号：US06222753B1

公开(公告)日：2001-04-24

申请号：US09446419

申请日：1999-12-20

申请人： Bernd Goebel ,  Emmerich Bertagnolli ,  Josef Willer ,  Barbara Hasler ,  Paul-Werner von Basse

发明人： Bernd Goebel ,  Emmerich Bertagnolli ,  Josef Willer ,  Barbara Hasler ,  Paul-Werner von Basse

IPC分类号： G11C700

CPC分类号： H01L27/11 ,  H01L27/1104

摘要： An SRAM cell arrangement which includes six MOS transistors per memory cell wherein each transistor is formed as a vertical transistors. The MOS transistors are arranged at sidewalls of trenches. Parts of the memory cell such as, for example, gate electrodes or conductive structures fashioned as spacers are contacted via adjacent, horizontal, conductive structures arranged above a surface of a substrate. Connections between parts of memory cells occur via third conductive structures arranged at the sidewalls of the depressions and word lines via diffusion regions that are adjacent to the sidewalls of the depressions within the substrate, via first bit lines, via second bit lines and/or via conductive structures that are partially arranged at different heights with respect to an axis perpendicular to the surface. Contacts contact a plurality of parts of the MOS transistors simultaneously.

摘要翻译： 每个存储单元包括六个MOS晶体管的SRAM单元布置，其中每个晶体管形成为垂直晶体管。 MOS晶体管布置在沟槽的侧壁。 存储单元的部分，例如栅极电极或形成为间隔物的导电结构，经由布置在衬底表面上方的相邻的水平导电结构接触。 存储器单元的部分之间的连接通过布置在凹陷和字线的侧壁处的第三导电结构经由第一位线经由第二位线和/或通孔的扩散区域经由衬底内的凹陷的侧壁相邻布置 相对于垂直于表面的轴部分地布置在不同高度的导电结构。 触头同时接触MOS晶体管的多个部分。

公开(公告)号：US6040995A

公开(公告)日：2000-03-21

申请号：US230614

申请日：1999-01-28

申请人： Hans Reisinger ,  Ulrike Gruning ,  Hermann Wendt ,  Reinhard Stengl ,  Volker Lehmann ,  Josef Willer ,  Martin Franosch ,  Herbert Schafer ,  Wolfgang Krautschneider ,  Franz Hofmann ,  Thomas Bohm

发明人： Hans Reisinger ,  Ulrike Gruning ,  Hermann Wendt ,  Reinhard Stengl ,  Volker Lehmann ,  Josef Willer ,  Martin Franosch ,  Herbert Schafer ,  Wolfgang Krautschneider ,  Franz Hofmann ,  Thomas Bohm

IPC分类号： H01L21/8247 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792 ,  H01L27/02

CPC分类号： H01L29/513 ,  H01L29/518 ,  H01L29/792

摘要： For the operation of a memory cell arrangement with MOS transistors as memory cells that comprise a dielectric triple layer (5) with a first silicon oxide layer (51), a silicon nitride layer (52) and a second silicon oxide layer (53) as gate dielectric, whereby the silicon oxide layers are respectively at least 3 nm thick, a first cutoff voltage value is allocated to a first logical value and a second cutoff voltage value of the MOS transistor is allocated to a second logical value for storing digital data. The information stored in the memory cell can be modified by applying corresponding voltage levels, although a complete removal of charge stored in the silicon nitride layer is not possible because of the thickness of the silicon oxide layers. What is exploited when modifying the cutoff voltage is that the electrical field in the dielectric triple layer is distorted by charge stored in the silicon nitride layer.

摘要翻译： PCT No.PCT / DE97 / 01601 Sec。 371日期1999年1月28日 102（e）1999年1月28日PCT PCT 1997年7月29日PCT公布。 出版物WO98 / 06140 日期1998年2月12日对于具有MOS晶体管的存储单元布置的操作，作为包含具有第一氧化硅层（51）的介电三层（5）的存储单元，具有氮化硅层（52）和第二氧化硅 层（53）作为栅极电介质，由此氧化硅层​​分别为至少3nm厚，将第一截止电压值分配给第一逻辑值，并将MOS晶体管的第二截止电压值分配给第二逻辑值 用于存储数字数据。 存储在存储单元中的信息可以通过施加相应的电压电平来修改，尽管由于氧化硅层的厚度，不可能完全去除存储在氮化硅层中的电荷。 当修改截止电压时，利用的是电介质三层中的电场由存储在氮化硅层中的电荷而失真。

公开(公告)号：US6033534A

公开(公告)日：2000-03-07

申请号：US54200

申请日：1993-04-30

申请人： Josef Willer ,  Hermann Wendt ,  Volker Lehmann

发明人： Josef Willer ,  Hermann Wendt ,  Volker Lehmann

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/334 ,  C23C14/34

CPC分类号： H01L29/66181 ,  H01L21/28512

摘要： A method for producing an Al-containing layer having a planar surface onto a substrate having hole structures with high aspect ratios formed in the surface of the substrate, wherein the Al-containing layer is applied in a sputtering process during which the substrate is held at an elevated temperature and the sputtering process is implemented at a pressure between 1.3.times.10.sup.-2 Pa and 13 Pa and at a low partial gas pressure. The substrate can be held at a temperature between approximately 400.degree. C. and 500.degree. C. during the sputtering process. A partial residual gas pressure of less than 1.3.times.10.sup.-5 PA can prevail in the vacuum. An intermediate layer of pure titanium and a barrier layer of TiN can be directly deposited onto the substrate and the Al-containing layer can then be applied onto this intermediate end barrier layer.

摘要翻译： 一种在基板的表面形成具有高纵横比的孔结构的基板上的具有平坦表面的含Al层的方法，其中所述含Al层以基板保持在其中的溅射工艺 升高的温度和溅射过程在1.3×10 -2 Pa至13 Pa之间的压力下和在低的部分气体压力下实施。 在溅射过程中，衬底可保持在约400℃至500℃的温度。 小于1.3×10-5PA的部分残余气体压力可以在真空中占优势。 可以将纯钛的中间层和TiN的阻挡层直接沉积到衬底上，然后将含Al层施加到该中间阻挡层上。

公开(公告)号：US5882969A

公开(公告)日：1999-03-16

申请号：US967419

申请日：1997-11-11

申请人： Wolfgang Krautschneider ,  Franz Hofmann ,  Hans Reisinger ,  Josef Willer

发明人： Wolfgang Krautschneider ,  Franz Hofmann ,  Hans Reisinger ,  Josef Willer

IPC分类号： H01L21/822 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L27/11521 ,  H01L21/8221 ,  H01L27/11551

摘要： In a method for manufacturing an electrically writeable and erasable ad-only memory cell arrangement, by self-adjusting process steps, a read-only memory cell arrangement having memory cells that respectively comprise an MOS transistor with a floating gate is manufactured. The MOS transistors are arranged in rows that run parallel. Adjacent rows thus respectively run alternately on the bottom of longitudinal trenches and between adjacent longitudinal trenches. The control gates laterally surround the floating gates so that the memory cells on the bottom of the longitudinal trenches also comprise a coupling ratio>1. A surface requirement per memory cell of 2F.sup.2 (F minimum structural size) is achieved.

摘要翻译： 在通过自调整处理步骤制造电可写和可擦除的仅ad的存储单元布置的方法中，制造了具有分别包括具有浮置栅极的MOS晶体管的存储单元的只读存储单元布置。 MOS晶体管排列成并行的行。 因此，相邻的行分别在纵向沟槽的底部和相邻的纵向沟槽之间交替地行进。 控制门横向围绕浮动栅极，使得纵向沟槽底部的存储单元也包括耦合比> 1。 实现2F2（F最小结构尺寸）每个存储单元的表面要求。

公开(公告)号：US5306647A

公开(公告)日：1994-04-26

申请号：US998611

申请日：1992-12-30

申请人： Volker Lehmann ,  Reinhard Stengl ,  Hermann Wendt ,  Wolfgang Hoenlein ,  Josef Willer

发明人： Volker Lehmann ,  Reinhard Stengl ,  Hermann Wendt ,  Wolfgang Hoenlein ,  Josef Willer

IPC分类号： C25F3/12 ,  H01L21/3063 ,  H01L31/0352 ,  H01L31/047 ,  H01L31/18

CPC分类号： H01L31/1804 ,  H01L21/3063 ,  H01L31/03529 ,  H01L31/047 ,  Y02E10/547 ,  Y02P70/521

摘要： A self-supporting layer of n-doped monocrystalline silicon is stripped from a substrate wafer of n-doped, monocrystalline silicon by electrochemical etching for manufacturing a solar cell. Holes are formed in the substrate wafer by electrochemical etching, particularly in a fluoride-containing, acidic electrolyte wherein the substrate wafer is connected as an anode. When a depth of the holes that essentially corresponds to the thickness of the self-supporting layer is reached, the process parameters of the etching are modified such that the self-supporting layer is stripped as a consequence of the holes growing together. The solar cell is manufactured from the self-supporting layer, and the method can be applied repeatedly on the same substrate wafer for stripping a plurality of self-supporting layers.

摘要翻译： 通过用于制造太阳能电池的电化学蚀刻，从n掺杂的单晶硅的衬底晶片剥离n掺杂单晶硅的自支撑层。 通过电化学蚀刻，特别是在其中衬底晶片作为阳极连接的含氟化物的酸性电解质中，在衬底晶片中形成孔。 当达到基本上对应于自支撑层的厚度的孔的深度时，蚀刻的工艺参数被修改，使得自支撑层由于孔一起生长而被剥离。 该太阳能电池由自支撑层制造，并且可以在相同的基板晶片上重复地施加该方法以剥离多个自支撑层。

公开(公告)号：US07875516B2

公开(公告)日：2011-01-25

申请号：US11855695

申请日：2007-09-14

申请人： Roman Knoefler ,  Michael Specht ,  Josef Willer

发明人： Roman Knoefler ,  Michael Specht ,  Josef Willer

IPC分类号： H01L21/8234

CPC分类号： H01L27/11568 ,  H01L21/823828 ,  H01L27/105 ,  H01L27/11573

摘要： An integrated circuit including a first gate stack and a second gate stack and a method of manufacturing is disclosed. One embodiment provides non-volatile memory cells including a first gate stack and a gate dielectric on a first surface section of a main surface of a semiconductor substrate, and a second gate stack including a memory layer stack on a second surface section. A first pattern is transferred into the first gate stack and a second pattern into the second gate stack.

摘要翻译： 公开了一种包括第一栅极堆叠和第二栅极堆叠的集成电路及其制造方法。 一个实施例提供包括在半导体衬底的主表面的第一表面部分上的第一栅极堆叠和栅极电介质的非易失性存储器单元，以及包括在第二表面部分上的存储层堆叠的第二栅极堆叠。 将第一图案转移到第一栅极堆叠中，将第二图案转移到第二栅极堆叠中。

公开(公告)号：US07868415B2

公开(公告)日：2011-01-11

申请号：US12177930

申请日：2008-07-23

申请人： Josef Willer ,  Michael Specht ,  Christoph Friederich ,  Doris Keitel-Schulz

发明人： Josef Willer ,  Michael Specht ,  Christoph Friederich ,  Doris Keitel-Schulz

IPC分类号： H01L23/58

CPC分类号： H01L21/28273 ,  H01L21/3086 ,  H01L21/32139 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/66825 ,  H01L29/7881

摘要： An integrated circuit is described. The integrated circuit may have: an active area line formed of a material of a semiconductor substrate with a first longitudinal direction parallel to an upper surface of the semiconductor substrate; wherein the active area line has at least one form-supporting element extending in a second longitudinal direction parallel to the upper surface of the semiconductor substrate; and wherein the second longitudinal direction is arranged with regard to the first longitudinal direction in an angle unequal to 0 degree and unequal to 180 degree.

摘要翻译： 描述了集成电路。 集成电路可以具有：由具有与半导体衬底的上表面平行的第一纵向方向的半导体衬底的材料形成的有源区线; 其中所述有源面积线具有至少一个形状支撑元件，所述支撑元件在平行于所述半导体衬底的上表面的第二纵向方向上延伸; 并且其中所述第二纵向方向相对于所述第一纵向方向以不等于0度并且不等于180度的角度布置。

公开(公告)号：US07790516B2

公开(公告)日：2010-09-07

申请号：US11483968

申请日：2006-07-10

申请人： Josef Willer ,  Nicolas Nagel

发明人： Josef Willer ,  Nicolas Nagel

IPC分类号： H01L21/82

CPC分类号： H01L29/7881 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568 ,  H01L29/792

摘要： A method of manufacturing at least one NAND-coupled semiconductor component is disclosed. A layer structure is formed on or above a semiconductor substrate. The layer structure is patterned to expose at least one region to be doped. The exposed region is doped and annealed. The patterned layer structure is at least partially removed. Replacing material is formed in the region in which the patterned layer structure has been removed, thereby forming the at least one NAND-coupled semiconductor component.

摘要翻译： 公开了制造至少一个NAND耦合的半导体部件的方法。 在半导体衬底上或上方形成层结构。 图案化层结构以暴露待掺杂的至少一个区域。 曝光区域被掺杂并退火。 图案化层结构至少部分地被去除。 在去除图案层结构的区域中形成更换材料，从而形成至少一个NAND耦合的半导体部件。

公开(公告)号：US07741630B2

公开(公告)日：2010-06-22

申请号：US12028513

申请日：2008-02-08

申请人： Klaus-Dieter Ufert ,  Josef Willer

发明人： Klaus-Dieter Ufert ,  Josef Willer

IPC分类号： H01L47/00

CPC分类号： H01L27/101 ,  H01L27/222 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/149 ,  H01L45/1625 ,  H01L45/1675

摘要： An integrated circuit including a memory cell and a method of manufacturing the integrated circuit are described. The memory cell includes a buried gate select transistor and a resistive memory element coupled to the buried gate select transistor. The resistive memory element stores information based on a resistivity of the resistive memory element.

摘要翻译： 描述了包括存储单元的集成电路和集成电路的制造方法。 存储单元包括掩埋栅极选择晶体管和耦合到掩埋栅选择晶体管的电阻存储元件。 电阻性存储元件基于电阻式存储元件的电阻率存储信息。