Field-effect transistor having a high packing density and method for fabricating it
    61.
    发明授权
    Field-effect transistor having a high packing density and method for fabricating it 失效
    具有高填充密度的场效应晶体管及其制造方法

    公开(公告)号:US06384456B1

    公开(公告)日:2002-05-07

    申请号:US09538793

    申请日:2000-03-30

    申请人: Jenoe Tihanyi

    发明人: Jenoe Tihanyi

    IPC分类号: H01L21265

    摘要: A field-effect transistor has a semiconductor body with a main area, in which at least one source zone and one drain zone are introduced and which is provided with a gate electrode isolated from a channel region disposed between a source zone and a drain zone by an insulator layer. In the field-effect transistor, the source zone, the drain zone and the channel region are disposed in walls of a respective trench or recess formed in the semiconductor body.

    摘要翻译: 场效应晶体管具有主要区域的半导体主体,其中引入至少一个源极区和一个漏极区,并且其中设置有栅极,该栅电极与设置在源极区和漏极区之间的沟道区隔离, 绝缘体层。 在场效应晶体管中,源极区,漏极区和沟道区设置在形成在半导体本体中的相应沟槽或凹槽的壁中。

    Bipolar transistor which can be controlled by field effect and method for producing the same
    63.
    发明授权
    Bipolar transistor which can be controlled by field effect and method for producing the same 有权
    可通过场效应控制的双极晶体管及其制造方法

    公开(公告)号:US06309920B1

    公开(公告)日:2001-10-30

    申请号:US09462760

    申请日:2000-04-10

    IPC分类号: H01L218238

    CPC分类号: H01L29/7395

    摘要: A method for forming a field effect vertical bipolar transistor that includes a semiconductive body that has at its top surface a plurality of emitter zones of one conductivity type, each surrounded by a base zone of the opposite conductivity type, and gate electrodes for creating a channel at the surface through the base zone into the bulk inner portion of the one conduction type and at a bottom surface a collector zone that includes a collector electrode overlying a collector layer of the opposite conduction type overlying a field stop layer heavily doped of the opposite conduction type overlying the inner portion lightly doped of the one conduction type. Each of the collector layer and the field stop layer is less than 2 microns in thickness and the collector layer is used to inject minority carriers into the inner zone when appropriately biased.

    摘要翻译: 一种用于形成场效应垂直双极晶体管的方法,其包括半导体,该半导体在其顶表面上具有一个导电类型的多个发射区,每个由相反导电类型的基极区围绕,并且用于产生沟道 在通过基底区域的表面进入一个导电类型的本体内部部分和在底部表面处的收集器区域,该收集器区域包括覆盖相反导电类型的集电极层的集电极电极,该集电极层覆盖重掺杂相反导电 类型覆盖轻度掺杂的一种导电类型的内部部分。 集电极层和场停止层中的每一个的厚度小于2微米,并且当适当偏置时,集电极层用于将少数载流子注入内部区域。

    Method for producing a field-effect-controllable, vertical semiconductor component
    64.
    发明授权
    Method for producing a field-effect-controllable, vertical semiconductor component 有权
    用于制造场效应可控垂直半导体元件的方法

    公开(公告)号:US06284604B1

    公开(公告)日:2001-09-04

    申请号:US09314192

    申请日:1999-05-19

    申请人: Jenoe Tihanyi

    发明人: Jenoe Tihanyi

    IPC分类号: H01L21336

    摘要: A field-effect-controllable, vertical semiconductor component, and a method for producing the semiconductor component include a semiconductor body having at least one drain zone of a first conduction type, at least one source zone of the first conduction type, at least one gate electrode insulated from the entire semiconductor body by a gate oxide, and a bulk region of the first conduction type. A source terminal is located on the rear side of the wafer, and a drain terminal and a gate terminal are located on the front side of the wafer.

    摘要翻译: 场效应可控的垂直半导体部件和用于制造半导体部件的方法包括半导体本体,其具有至少一个第一导电类型的漏极区域,至少一个第一导电类型的源极区域,至少一个栅极 电极通过栅极氧化物与整个半导体本体绝缘,以及第一导电类型的主体区域。 源极端子位于晶片的后侧,漏极端子和栅极端子位于晶片的前侧。

    Field effect controlled semiconductor component
    65.
    发明授权
    Field effect controlled semiconductor component 失效
    场效应控制半导体元件

    公开(公告)号:US5869864A

    公开(公告)日:1999-02-09

    申请号:US834311

    申请日:1997-04-15

    申请人: Jenoe Tihanyi

    发明人: Jenoe Tihanyi

    摘要: A semiconductor component having a body with an upper surface, a base zone having a portion adjoining the upper surface of the semiconductor body, at least one source zone embedded in the base zone, at least one gate electrode lying parallel to the upper surface that covers at least the portion of the base zone adjoining the upper surface, a contact region constructed and arranged as a buried layer in the base zone and projecting laterally beyond the source zone, the contact region having a higher conductivity than that of the base zone, and an electrode that contacts the source zone and the contact region. In order to improve the contact between base zone and source electrode, the contact region is fashioned as a layer buried in the base zone and projects laterally beyond the source zone. Also, a field effect controlled semiconductor component having at least one source zone, at least one vertical gate electrode arranged in a trench lying vertically relative to the surface, at least one base zone that laterally abuts the trench, a contact region having a depth greater than that of the source zone and a conductivity higher than that of the base zone and is electrically connected thereto, and an electrode that contacts the source zone and the contact region.

    摘要翻译: 一种具有上表面的主体的半导体部件,具有邻接半导体主体的上表面的部分的基区,至少一个嵌入基区的源极区,平行于上表面的至少一个栅电极, 所述基部区域的至少部分邻接所述上表面,所述接触区域被构造并布置为所述基底区域中的掩埋层并且横向突出超出所述源极区域,所述接触区域具有比所述基底区域更高的导电性,以及 接触源区和接触区的电极。 为了改善基区和源电极之间的接触,接触区被形成为埋在基区中的层,横向突出超出源区。 此外,具有至少一个源极区域的至少一个源区域的场效应控制半导体元件,布置在相对于该表面垂直放置的沟槽中的至少一个垂直栅极电极,横向邻接沟槽的至少一个基极区域,具有更大深度的接触区域 并且电导率高于基极区的电导率,并且电连接到其上,以及接触源极区和接触区的电极。

    Integrated comparator circuit
    66.
    发明授权
    Integrated comparator circuit 失效
    集成比较电路

    公开(公告)号:US5834954A

    公开(公告)日:1998-11-10

    申请号:US679251

    申请日:1996-07-12

    申请人: Jenoe Tihanyi

    发明人: Jenoe Tihanyi

    CPC分类号: G01R19/16519

    摘要: An integrated comparator circuit includes a first terminal and a second terminal for an operating voltage. An input stage has two complementary MOSFETS having main current paths connected in series defining a common connecting point therebetween. The two MOSFETS have gate terminals connected to the common connecting point. The series circuit of the MOSFETS is connected between the first terminal and a third terminal. An inverter stage has two complementary MOSFETS having main current paths connected in series defining a common connecting point therebetween forming an output terminal. The two complementary MOSFETS have gate terminals connected to the common connecting point of the input stage. The second terminal and the third terminal receive an input signal of the comparator circuit. A fourth terminal is provided for application of a reference potential to determine a switching threshold of the comparator circuit. The reference potential has a level between potentials of the first terminal and the second terminal. The series circuit of the MOSFETs of the inverter stage is connected between the first terminal and the fourth terminal. Each of the MOSFETs of the same channel type are identical.

    摘要翻译: 集成比较器电路包括用于工作电压的第一端子和第二端子。 输入级具有两个互补MOSFET,其主电流路径串联连接,限定了它们之间的公共连接点。 两个MOSFET都具有连接到公共连接点的栅极端子。 MOSFETS的串联电路连接在第一端子和第三端子之间。 逆变器级具有两个互补MOSFET,其主电流路径串联连接,形成一个共同的连接点,形成输出端。 两个互补MOSFETs的栅极端子连接到输入级的公共连接点。 第二端子和第三端子接收比较器电路的输入信号。 提供第四端子用于施加参考电位以确定比较器电路的开关阈值。 参考电位具有第一端子和第二端子的电位之间的电平。 逆变器级的MOSFET的串联电路连接在第一端子和第四端子之间。 相同通道类型的每个MOSFET是相同的。

    Circuit configuration for triggering a power enhancement MOSFET
    67.
    发明授权
    Circuit configuration for triggering a power enhancement MOSFET 失效
    用于触发功率增强MOSFET的电路配置

    公开(公告)号:US5798666A

    公开(公告)日:1998-08-25

    申请号:US721547

    申请日:1996-09-26

    申请人: Jenoe Tihanyi

    发明人: Jenoe Tihanyi

    CPC分类号: H03K17/063 H03K17/04123

    摘要: Power MOSFETs with a source-side load are often triggered by so-called charge pumps. In order to provide a faster turnoff, until now the gate-to-source capacitance of the power MOSFET, which is typically constructed as an enhancement MOSFET, has been discharged through a depletion MOSFET that is parallel to the gate-to-source path. Those different MOSFET types require complicated and expensive production technology. A circuit configuration is proposed that makes it possible to use solely enhancement MOSFETs.

    摘要翻译: 具有源极负载的功率MOSFET通常由所谓的电荷泵触发。 为了提供更快的关断,到目前为止,通常被构造为增强型MOSFET的功率MOSFET的栅极 - 源极电容已经通过与栅极到源极路径平行的耗尽MOSFET放电。 这些不同的MOSFET类型需要复杂和昂贵的生产技术。 提出了使得可以仅使用增强型MOSFET的电路配置。

    Circuit configuration for detecting idling of a load
    68.
    发明授权
    Circuit configuration for detecting idling of a load 失效
    用于检测负载怠速的电路配置

    公开(公告)号:US5736877A

    公开(公告)日:1998-04-07

    申请号:US715425

    申请日:1996-09-18

    申请人: Jenoe Tihanyi

    发明人: Jenoe Tihanyi

    CPC分类号: H03K17/18 H02H3/12

    摘要: In power switches, reports should be issued frequently when the load becomes high in impedance and the load current drops below a predetermined value. In the idling case, however, the voltage drop at the power switch is very low and therefore can only be measured with some inaccuracy. Accurate detection of the reduction in the load current is possible, if a resistor is connected parallel, in the ON-state, to the load path of the power switch. The resistance of the resistor is greater by a multiple than the resistance of the internal resistor of the load path of the power switch. A comparator compares the voltage dropping at the load path of the power switch and therefore at the resistor with a predetermined reference voltage, and it signals the dropping of the load current below a value defined by the ratio of the reference voltage and the resistance of the resistor.

    摘要翻译: 在电源开关中,当负载变得高阻抗并且负载电流下降到预定值以下时,应频繁地发出报告。 然而,在空转情况下,电源开关处的电压降非常低,因此只能用一些不准确的方法进行测量。 如果在接通状态下将电阻并联连接到电源开关的负载路径,则可以准确检测负载电流的降低。 电阻的电阻比电源开关负载路径的内部电阻的电阻大一倍。 比较器比较电源开关的负载路径上的电压下降以及在电阻器处的电压下降到预定的参考电压,并且将负载电流的下降信号指示为由参考电压和电阻的比值所限定的值 电阻。

    Power semiconductor component with temperature sensor
    69.
    发明授权
    Power semiconductor component with temperature sensor 失效
    功率半导体元件带温度传感器

    公开(公告)号:US5638021A

    公开(公告)日:1997-06-10

    申请号:US376249

    申请日:1995-01-23

    摘要: A power semiconductor component assembly includes a power semiconductor component having a semiconductor body. A controllable switch is connected to the power semiconductor component. A temperature sensor has a given reset time. The temperature sensor is connected to the controllable switch for turning on the controllable switch to control the power semiconductor component from a conducting state into a range of higher resistance once a temperature in the semiconductor body of the power semiconductor component attains a critical value. A delay member is connected between the temperature sensor and the controllable switch. The delay member is triggered upon response of the temperature sensor and has a delay time being longer than the given reset time, for preventing blocking of the controllable switch during the delay time.

    摘要翻译: 功率半导体部件组件包括具有半导体本体的功率半导体部件。 可控开关连接到功率半导体部件。 温度传感器具有给定的复位时间。 温度传感器连接到可控开关,用于接通可控开关,一旦功率半导体元件的半导体主体中的温度达到临界值,则将功率半导体部件从导通状态控制到较高电阻的范围内。 延迟构件连接在温度传感器和可控开关之间。 延迟构件在温度传感器的响应时触发,并且具有比给定的复位时间长的延迟时间,以防止在延迟时间期间阻塞可控开关。

    Integrable buffer circuit for voltage level conversion having clamping
means
    70.
    发明授权
    Integrable buffer circuit for voltage level conversion having clamping means 失效
    具有钳位装置的用于电压电平转换的可积分缓冲电路

    公开(公告)号:US4801824A

    公开(公告)日:1989-01-31

    申请号:US76255

    申请日:1987-07-21

    摘要: A signal voltage (E) based upon a supply voltage must be converted to a signal voltage (A) with ground reference so as to enable further processing in a logic circuit. A simple level converter comprises a series connection of a MOSFET (T1) connected to the supply voltage; the MOSFET also comprises a resistor (T2). The source terminal of the MOSFET (T1) is located at the potential of the supply voltage. The voltage to be converted is applied between the gate terminal and the source terminal, and the converted voltage occurs at the resistor (T2). The two voltages are each limited by one Zener diode (D2, D1).

    摘要翻译: 基于电源电压的信号电压(E)必须被转换为具有接地参考的信号电压(A),以便能够在逻辑电路中进一步处理。 简单的电平转换器包括连接到电源电压的MOSFET(T1)的串联连接; MOSFET还包括电阻器(T2)。 MOSFET(T1)的源极端子位于电源电压的电位。 要转换的电压施加在栅极端子和源极端子之间,转换的电压发生在电阻器(T2)处。 两个电压都由一个齐纳二极管(D2,D1)限制。