公开(公告)号：US08508621B2

公开(公告)日：2013-08-13

申请号：US12895346

申请日：2010-09-30

申请人： Guy Côté ,  Jeffrey E. Frederiksen ,  Joseph P. Bratt ,  Jung Wook Cho

发明人： Guy Côté ,  Jeffrey E. Frederiksen ,  Joseph P. Bratt ,  Jung Wook Cho

IPC分类号： H04N5/76

CPC分类号： H04N5/772 ,  H04N5/23229 ,  H04N5/23235 ,  H04N5/2354 ,  H04N5/3572 ,  H04N5/367 ,  H04N9/045 ,  H04N9/735 ,  H04N19/80

摘要： Certain embodiments of the present disclosure provide a flexible memory input/output controller that is configured to the storing and reading of multiple types of pixels and pixel memory formats. For instance, the memory I/O controller may support the storing and reading of raw image pixels at various bits of precision, such as 8-bit, 10-bit, 12-bit, 14-bit, and 16-bit. Pixel formats that are unaligned with memory bytes (e.g., not being a multiple of 8-bits) may be stored in a packed manner. The memory I/O controller may also support various formats of RGB pixel sets and YCC pixel sets.

摘要翻译： 本公开的某些实施例提供了一种灵活的存储器输入/输出控制器，其被配置为存储和读取多种类型的像素和像素存储器格式。 例如，存储器I / O控制器可以支持以各种精度位（例如8位，10位，12位，14位和16位）存储和读取原始图像像素。 与存储器字节不对齐的像素格式（例如，不是8位的倍数）可以以打包的方式存储。 存储器I / O控制器还可以支持RGB像素集和YCC像素集的各种格式。

公开(公告)号：US08405668B2

公开(公告)日：2013-03-26

申请号：US12950293

申请日：2010-11-19

申请人： Joseph P. Bratt ,  Peter F. Holland

发明人： Joseph P. Bratt ,  Peter F. Holland

IPC分类号： G06F12/00 ,  G06F12/02 ,  G06F12/10

CPC分类号： G06F12/0215 ,  G06F12/0802 ,  G06F12/0862 ,  G06F12/1027 ,  G06F12/123 ,  G06F2212/302 ,  G06F2212/654

摘要： In an embodiment, a display pipe includes one or more translation units corresponding to images that the display pipe is reading for display. Each translation unit may be configured to prefetch translations ahead of the image data fetches, which may prevent translation misses in the display pipe (at least in most cases). The translation units may maintain translations in first-in, first-out (FIFO) fashion, and the display pipe fetch hardware may inform the translation unit when a given translation or translation is no longer needed. The translation unit may invalidate the identified translations and prefetch additional translation for virtual pages that are contiguous with the most recently prefetched virtual page.

公开(公告)号：US20120127364A1

公开(公告)日：2012-05-24

申请号：US12950185

申请日：2010-11-19

申请人： Joseph P. Bratt ,  Peter F. Holland

发明人： Joseph P. Bratt ,  Peter F. Holland

IPC分类号： H04N7/01

CPC分类号： H04N9/67 ,  G09G2340/06

摘要： A display pipe may include a video pipe outputting pixels of a video stream in a first color space, e.g. YCbCr color space. The display pipe may also include a first color space converter to convert the output pixels to a second color space, e.g. to RGB color space, producing a conversion output in which some of the converted output pixels have values that are invalid pixel values in the second color space. The display pipe may also include a blend unit that performs blending operations in the second color space on the converted output pixels to produce a blended conversion output that includes blended pixels in the second color space. A second color space converter in the display pipe may convert the blended pixels from the second color space to the first color space, and correctly display the converted blended pixels on a display screen.

摘要翻译： 显示管可以包括输出第一颜色空间中的视频流的像素的视频管，例如。 YCbCr颜色空间。 显示管还可以包括第一颜色空间转换器，以将输出像素转换为第二颜色空间，例如， 到RGB颜色空间，产生转换输出，其中一些转换的输出像素具有在第二颜色空间中的无效像素值的值。 显示管还可以包括混合单元，其在转换的输出像素上的第二颜色空间中执行混合操作，以产生包括第二颜色空间中的混合像素的混合转换输出。 显示管中的第二颜色空间转换器可以将混合像素从第二颜色空间转换为第一颜色空间，并将转换的混合像素正确显示在显示屏上。

公开(公告)号：US20120026368A1

公开(公告)日：2012-02-02

申请号：US12846008

申请日：2010-07-29

申请人： Guy Côté ,  Jeffrey E. Frederiksen ,  Joseph P. Bratt

发明人： Guy Côté ,  Jeffrey E. Frederiksen ,  Joseph P. Bratt

IPC分类号： H04N9/64

CPC分类号： G06T3/4015

摘要： Various techniques for applying binning compensation filtering to binned raw image data acquired by an image sensor are provided. In one embodiment, a binning compensation filter (BCF) includes separate digital differential analyzers (DDA) for vertical and horizontal scaling. A current position of an output pixel is determined by incrementing the DDA based upon a step size. Using the known output pixel position, a center source input pixel and an index corresponding to the between-pixel fractional position of the output pixel position relative to the input pixels may be selected for filtering. Using the selected center input pixel, one or more same-colored neighboring source pixels may be selected. The number of selected source pixels may depend on the number of taps used by the scaling logic, and may depend on whether horizontal or vertical scaling is being applied. Using the selected index, a set of filter coefficients may be selected from a filter coefficient lookup table, applied to the selected source pixels, and the results may be summed to determine a value for an output pixel having a position corresponding to the current position of the DDA. This process may be repeated for each input pixel and may be performed in both vertical and horizontal directions, thus ultimately producing a re-sampled set of image data that is spatially evenly distributed.

摘要翻译： 提供了用于将分档补偿滤波应用于由图像传感器获取的二进制原始图像数据的各种技术。 在一个实施例中，分箱补偿滤波器（BCF）包括用于垂直和水平缩放的单独的数字差分分析器（DDA）。 通过基于步长增加DDA来确定输出像素的当前位置。 使用已知的输出像素位置，可以选择中心源输入像素和对应于输出像素位置相对于输入像素的像素间分数位置的索引用于滤波。 使用所选择的中心输入像素，可以选择一个或多个相同颜色的相邻源像素。 选择的源像素的数量可以取决于缩放逻辑使用的抽头的数量，并且可以取决于是否应用水平或垂直缩放。 使用所选择的索引，可以从应用于所选择的源像素的滤波器系数查找表中选择一组滤波器系数，并且将结果相加以确定具有对应于当前位置的位置的输出像素的值 DDA。 对于每个输入像素可以重复该过程，并且可以在垂直和水平方向上执行该过程，从而最终产生在空间上均匀分布的重新采样的图像数据集。

公开(公告)号：US20110169849A1

公开(公告)日：2011-07-14

申请号：US12685171

申请日：2010-01-11

申请人： Joseph P. Bratt ,  Shing Choo ,  Peter F. Holland ,  Timothy J. Millet ,  Brijesh Tripathi

发明人： Joseph P. Bratt ,  Shing Choo ,  Peter F. Holland ,  Timothy J. Millet ,  Brijesh Tripathi

IPC分类号： G09G5/36

CPC分类号： G06T1/60 ,  G09G5/39

摘要： A graphics system may include a display pipe with a buffer configured to store pixels to be processed by a display controller for displaying on a display device, with a buffer control circuit coupled to the buffer to supply pixels to the display controller. When the buffer control circuit detects an underrun of the buffer responsive to the display controller attempting to read pixels from the buffer that have not yet been written to the buffer, the buffer control circuit may supply an underrun pixel to the display. The underrun pixel may be selected from a set of previously stored set of underrun pixels, which may include a most recent valid pixel read by the display controller. A read pointer representative of the location in the buffer from where the display controller is currently attempting to read may be advanced even when an underrun condition occurs. The underrun pixel may be supplied to the display controller until the underrun has been resolved, at which point the most recent valid pixel read from the buffer may be supplied to the display controller.

摘要翻译： 图形系统可以包括具有缓冲器的显示管道，缓冲器被配置为存储要由显示控制器处理的像素，用于在显示设备上显示，缓冲器控制电路耦合到缓冲器以向显示控制器提供像素。 当缓冲器控制电路响应于显示控制器尝试读取尚未写入缓冲器的缓冲器的像素时，缓冲器控制电路检测到欠载，缓冲器控制电路可以向显示器提供欠载像素。 欠载像素可以从先前存储的欠载像素组中选择，其可以包括由显示控制器读取的最新有效像素。 即使在出现欠载条件的情况下，代表显示控制器当前尝试读取的缓冲器中的位置的读取指针也可以被提前。 欠载像素可以被提供给显示控制器，直到欠载已被解析为止，此时从缓冲器读取的最新的有效像素可以被提供给显示控制器。

公开(公告)号：US20110169848A1

公开(公告)日：2011-07-14

申请号：US12685166

申请日：2010-01-11

申请人： Joseph P. Bratt ,  Shing Choo ,  Peter F. Holland ,  Timothy J. Millet

发明人： Joseph P. Bratt ,  Shing Choo ,  Peter F. Holland ,  Timothy J. Millet

IPC分类号： G09G5/36

CPC分类号： G06T1/60 ,  G09G5/14 ,  G09G5/363 ,  G09G2340/10 ,  G09G2360/12 ,  G09G2360/127

摘要： A graphics system may include one or more processing units for processing a current display frame, each processing unit including a plurality of parameter registers for storing parameter settings used in processing the current display frame. A parameter buffer in the graphics system may store frame packets, with each frame packet containing information corresponding to parameter settings to be used for at least one display frame. A control circuit coupled to the buffer and to the one or more processing units may retrieve and process a top frame packet from the parameter buffer to update one or more of the parameter registers according to the contents of the top frame packet. The control circuit may issue DMA requests to fill the parameter buffer with frame packets transferred from system memory, where the frame packets may be written by an application (or software) executing on a central processing unit.

摘要翻译： 图形系统可以包括用于处理当前显示帧的一个或多个处理单元，每个处理单元包括用于存储用于处理当前显示帧的参数设置的多个参数寄存器。 图形系统中的参数缓冲器可以存储帧分组，每个帧分组包含对应于要用于至少一个显示帧的参数设置的信息。 耦合到缓冲器和一个或多个处理单元的控制电路可以从参数缓冲器检索和处理顶部帧分组，以根据顶部帧分组的内容更新一个或多个参数寄存器。 控制电路可以发出DMA请求，用从系统存储器传送的帧分组填充参数缓冲器，其中帧分组可以由在中央处理单元上执行的应用（或软件）写入。

公开(公告)号：US20110169847A1

公开(公告)日：2011-07-14

申请号：US12685152

申请日：2010-01-11

申请人： Joseph P. Bratt ,  Shing Choo ,  Peter F. Holland ,  Timothy J. Millet

发明人： Joseph P. Bratt ,  Shing Choo ,  Peter F. Holland ,  Timothy J. Millet

IPC分类号： G09G5/36

CPC分类号： G06F3/14 ,  G09G5/14 ,  G09G5/397 ,  G09G2340/10 ,  G09G2360/12

摘要： A user interface unit in a graphics processing display pipe may include registers programmable with information that defines active regions of an image frame. Pixels within the active regions of the image frame are meant to be displayed, while pixels outside of the active regions of the image frame are not to be displayed. Fetch circuitry within the user interface unit may fetch frames from memory, fetching only the pixels within the active regions of the image frames as defined by the programmed contents of the registers. The user interface unit may then provide the fetched pixels to a blend unit to blend the fetched pixels with pixels from other frames or pixels of a video stream to produce output frames. When blended with pixels of a video stream, the fetched pixels may be displayed as a graphics overlay on top of the video stream.

摘要翻译： 图形处理显示管道中的用户界面单元可以包括可以定义图像帧的有效区域的信息来编程的寄存器。 旨在显示图像帧的有效区域内的像素，而不显示图像帧的有效区域之外的像素。 用户接口单元内的提取电路可以从存储器获取帧，仅获取由寄存器的编程内容定义的图像帧的有效区域内的像素。 然后，用户界面单元可以将获取的像素提供给混合单元，以将获取的像素与来自视频流的其他帧或像素的像素混合以产生输出帧。 当与视频流的像素混合时，获取的像素可以被显示为视频流顶部的图形覆盖。

公开(公告)号：US07653776B2

公开(公告)日：2010-01-26

申请号：US11304439

申请日：2005-12-14

申请人： William P. Cornelius ,  Paul A. Baker ,  Joseph P. Bratt

发明人： William P. Cornelius ,  Paul A. Baker ,  Joseph P. Bratt

IPC分类号： G06F3/00 ,  G06F13/00

CPC分类号： G06F1/22

摘要： A system that selectively couples one or more IC chips to card slots. The system contains a Z-bar switch which includes: a select input; a first IC port coupled to a first IC pin; a second IC port coupled to a second IC pin; a first card slot port coupled to a first card slot pin; and a second card slot port coupled to a second card slot pin. If the select input receives a first control pattern, the Z-bar switch is configured to: couple the first IC port to the first card slot port; and to couple the second IC port to the second card slot port. If the select input receives a second control pattern, the Z-bar switch is configured to: couple the first IC port to the second card slot port; leave the second IC port floating; and to leave the first card slot port floating.

摘要翻译： 将一个或多个IC芯片选择性地耦合到卡插槽的系统。 该系统包含一个Z-bar开关，它包括：一个选择输入; 耦合到第一IC引脚的第一IC端口; 耦合到第二IC引脚的第二IC端口; 耦合到第一卡槽销的第一卡槽口; 以及耦合到第二卡槽销的第二卡槽口。 如果选择输入接收到第一控制模式，则Z-bar开关被配置为：将第一IC端口耦合到第一卡插槽端口; 并将第二IC端口耦合到第二卡槽口。 如果选择输入接收到第二控制模式，则Z-bar开关被配置为：将第一IC端口耦合到第二卡插槽端口; 离开第二个IC端口; 并离开第一个卡槽口浮动。

公开(公告)号：US20090248911A1

公开(公告)日：2009-10-01

申请号：US12057146

申请日：2008-03-27

申请人： DAVID G. CONROY ,  Timothy J. Millet ,  Joseph P. Bratt

发明人： DAVID G. CONROY ,  Timothy J. Millet ,  Joseph P. Bratt

IPC分类号： G06F1/12

CPC分类号： G06F13/34 ,  G06F1/12 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  G06F1/3287 ,  G06F13/1673 ,  G06F13/28 ,  Y02D10/126 ,  Y02D10/151 ,  Y02D10/171

摘要： A method and system is disclosed for accessing I/O and memory devices utilizing a DMA controller. Each device may be connected to the DMA controller through an individual channel. Clocking circuitry in the DMA may allow the DMA controller to send signals to each device at a prescribed frequency. Furthermore, the DMA controller is capable of activating and deactivating a channel clock, used in sending signals to the devices, based on the operational status of the individual devices. The DMA controller is also capable of tuning the channel clock dependant on the capabilities of any active devices. In this manner, the amount of bandwidth used during a DMA data transfer can be tailored to the specific requirements of the devices involved with the data transfer.

摘要翻译： 公开了一种利用DMA控制器访问I / O和存储器件的方法和系统。 每个设备可以通过单独的通道连接到DMA控制器。 DMA中的时钟电路可以允许DMA控制器以规定的频率向每个设备发送信号。 此外，DMA控制器能够基于各个设备的操作状态来激活和去激活用于向设备发送信号的通道时钟。 DMA控制器还能够根据任何有源器件的功能调整通道时钟。 以这种方式，DMA数据传输期间使用的带宽量可以根据与数据传输相关的设备的具体要求进行调整。

公开(公告)号：US07114058B1

公开(公告)日：2006-09-26

申请号：US10038383

申请日：2001-12-31

申请人： Sushma Shrikant Trivedi ,  Joseph P. Bratt ,  Jack Benkual ,  Ronald Ray Hochsprung ,  Derek Fujio Iwamoto

发明人： Sushma Shrikant Trivedi ,  Joseph P. Bratt ,  Jack Benkual ,  Ronald Ray Hochsprung ,  Derek Fujio Iwamoto

IPC分类号： G06F9/30

CPC分类号： G06F9/3853 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/3836 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3867 ,  G06F9/3879 ,  G06F9/3885

摘要： Methods and apparatuses for dispatching instructions executed by at least one functional unit of a data processor, each one of the instructions having a corresponding priority number, in a data processing system having at least one host processor with host processor cache and host memory are described herein. In one aspect of the invention, an exemplary method includes receiving a next instruction from an instruction stream, examining a current instruction group to determine if the current instruction group is completed, adding the next instruction to the current instruction group if the current instruction group is not completed, and dispatching the current instruction group if the current instruction group is completed.

摘要翻译： 本文描述了在具有至少一个具有主处理器高速缓存和主机存储器的主机处理器的数据处理系统中调度由数据处理器的至少一个功能单元执行的指令的方法和装置，每个指令具有相应的优先级号码 。 在本发明的一个方面，一种示例性方法包括从指令流接收下一条指令，检查当前指令组以确定当前指令组是否完成，如果当前指令组是 未完成，如果当前指令组完成，则调度当前指令组。