REDUCING READ DISTURB FOR NON-VOLATILE STORAGE

    公开(公告)号:US20080137411A1

    公开(公告)日:2008-06-12

    申请号:US12021761

    申请日:2008-01-29

    IPC分类号: G11C16/26

    CPC分类号: G11C16/3418 G11C16/3427

    摘要: A system is disclosed for reducing or removing a form of read disturb in a non-volatile storage device. One embodiment seeks to prevent read disturb by eliminating or minimizing boosting of the channel of the memory elements. For example, one implementation prevents or reduces boosting of the source side of the NAND string channel during a read process. Because the source side of the NAND string channel is not boosted, at least one form of read disturb is minimized or does not occur.

    Self-regulating process-error trimmable PTAT current source
    62.
    发明授权
    Self-regulating process-error trimmable PTAT current source 有权
    自调整过程误差可调PTAT电流源

    公开(公告)号:US07236048B1

    公开(公告)日:2007-06-26

    申请号:US11284583

    申请日:2005-11-22

    IPC分类号: G05F1/10

    CPC分类号: G05F3/30

    摘要: A current source for generating a PTAT current using two bipolar transistors with an 1:A emitter area ratio implements a split resistor architecture to cancel mismatch errors in the current mirror of the current source. In one embodiment, a first resistor is coupled to the unit area bipolar transistor and a second resistor is coupled to the A-ratio-area bipolar transistor. The first resistor has a resistance value indicative of the emitter resistance re of the bipolar transistors while the second resistor has a resistance value satisfying the equation re*(lnA−1). In another embodiment, an emitter area trim scheme is applied in a PTAT current source to cancel, in one trim operation, both bipolar transistor area mismatch error and sheet resistance variations. The emitter area trim scheme operates to modify the emitter area of the A-ratio-area bipolar transistor to select the best effective emitter area that provides the most accurate PTAT current.

    摘要翻译: 使用具有1:A发射极面积比的两个双极晶体管产生PTAT电流的电流源实现了分离电阻架构,以消除电流源的电流镜中的失配误差。 在一个实施例中,第一电阻器耦合到单位区域双极晶体管,并且第二电阻器耦合到A比区域双极晶体管。 第一电阻器具有指示双极晶体管的发射极电阻r e e的电阻值,而第二电阻器具有满足方程式的电阻值(1n-1) )。 在另一个实施例中,在PTAT电流源中施加发射极面积微调方案,以在一个微调操作中消除双极晶体管面积失配误差和薄层电阻变化。 发射极区域修整方案用于修改A比率面积双极晶体管的发射极面积,以选择提供最准确的PTAT电流的最佳有效发射极面积。

    Reducing read disturb for non-volatile storage
    63.
    发明申请
    Reducing read disturb for non-volatile storage 有权
    减少非易失性存储的读取干扰

    公开(公告)号:US20070133295A1

    公开(公告)日:2007-06-14

    申请号:US11295776

    申请日:2005-12-06

    IPC分类号: G11C16/06

    CPC分类号: G11C16/3418 G11C16/3427

    摘要: A system is disclosed for reducing or removing a form of read disturb in a non-volatile storage device. One embodiment seeks to prevent read disturb by eliminating or minimizing boosting of the channel of the memory elements. For example, one implementation prevents or reduces boosting of the source side of the NAND string channel during a read process. Because the source side of the NAND string channel is not boosted, at least one form of read disturb is minimized or does not occur.

    摘要翻译: 公开了一种用于减少或去除非易失性存储设备中的读取干扰形式的系统。 一个实施例旨在通过消除或最小化存储器元件的通道的升高来防止读取干扰。 例如,一个实施方式在读取过程期间防止或减少NAND串通道的源极侧的升压。 因为NAND串通道的源极侧不被提升,所以读取干扰的至少一种形式被最小化或不发生。

    Last-first mode and method for programming of non-volatile memory with reduced program disturb
    64.
    发明授权
    Last-first mode and method for programming of non-volatile memory with reduced program disturb 有权
    用于编程非易失性存储器的最后模式和方法,减少了程序干扰

    公开(公告)号:US07218552B1

    公开(公告)日:2007-05-15

    申请号:US11223623

    申请日:2005-09-09

    IPC分类号: G11C11/34 G11C16/06

    摘要: A non-volatile memory is programmed in a manner which reduces the incidence of program disturb for inhibited memory elements which undergo boosting to reduce program disturb, but which experience reduced boosting benefits due to their word line location. To achieve this result, a word line sequence in which the memory elements are programmed is adjusted so that higher word lines are programmed first, out of sequence relative to the remaining word lines. Additionally, self-boosting can be used for the higher word lines, while erased area self-boosting or a variant can be used for the remaining word lines. Furthermore, pre-charging of the channel of the inhibited memory elements may be employed prior to the self boosting, for the non-volatile storage elements which are programmed after those associated with the first word line.

    摘要翻译: 非易失性存储器被编程为减少对经过增强的抑制存储器元件的编程干扰的发生率以减少编程干扰的方式,但是哪些经验减少了由于其字线位置而引起的益处。 为了实现该结果,调整存储器元件被编程的字线序列,使得较高的字线首先被编程,而不是相对于剩余字线的顺序。 另外,自增强可以用于较高的字线,而擦除区域自增强或变体可用于剩余的字线。 此外,对于在与第一字线相关联的那些之后编程的非易失性存储元件,可以在自增强之前采用禁止的存储器元件的通道的预充电。

    System for programming non-volatile memory with self-adjusting maximum program loop
    65.
    发明申请
    System for programming non-volatile memory with self-adjusting maximum program loop 有权
    用于自适应最大程序循环编程非易失性存储器的系统

    公开(公告)号:US20070025156A1

    公开(公告)日:2007-02-01

    申请号:US11394441

    申请日:2006-03-31

    申请人: Jun Wan Jeffrey Lutze

    发明人: Jun Wan Jeffrey Lutze

    IPC分类号: G11C11/34 G11C16/04 G11C16/06

    摘要: The maximum allowable number of voltage programming pulses to program memory elements of a non-volatile memory device is adjusted to account for changes in the memory elements which occur over time. Programming pulses are applied until the threshold voltage of one or more memory elements reaches a certain verify level, after which a defined maximum number of additional pulses may be applied to other memory elements to allow them to also Teach associated target threshold voltage levels. The technique enforces a maximum allowable number of programming pulses that can change over time as the memory is cycled.

    摘要翻译: 调整非易失性存储器件对程序存储器元件的电压编程脉冲的最大允许数量,以便考虑随时间发生的存储元件的变化。 施加编程脉冲,直到一个或多个存储器元件的阈值电压达到某个验证电平,在此之后,定义的最大数量的附加脉冲可以被施加到其它存储器元件,以允许它们也教导相关联的目标阈值电压电平。 该技术实现了随着存储器循环而随时间变化的最大允许编程脉冲数。

    Method for programming non-volatile memory with self-adjusting maximum program loop
    66.
    发明授权
    Method for programming non-volatile memory with self-adjusting maximum program loop 有权
    用自调节最大程序循环编程非易失性存储器的方法

    公开(公告)号:US07161836B1

    公开(公告)日:2007-01-09

    申请号:US11194439

    申请日:2005-08-01

    IPC分类号: G11C11/34 G11C7/00

    摘要: The maximum allowable number of voltage programming pulses to program memory elements of a non-volatile memory device is adjusted to account for changes in the memory elements which occur over time. Programming pulses are applied until the threshold voltage of one or more memory elements reaches a certain verify level, after which a defined maximum number of additional pulses may be applied to other memory elements to allow them to also reach associated target threshold voltage levels. The technique enforces a maximum allowable number of programming pulses that can change over time as the memory is cycled.

    摘要翻译: 调整非易失性存储器件对程序存储器元件的电压编程脉冲的最大允许数量,以便考虑随时间发生的存储元件的变化。 施加编程脉冲,直到一个或多个存储器元件的阈值电压达到某个验证电平,之后可以将限定的最大数量的附加脉冲施加到其它存储器元件以允许它们也达到相关联的目标阈值电压电平。 该技术实现了随着存储器循环而随时间变化的最大允许编程脉冲数。

    Intelligent control of program pulse duration
    70.
    发明授权
    Intelligent control of program pulse duration 有权
    智能控制程序脉冲持续时间

    公开(公告)号:US07630249B2

    公开(公告)日:2009-12-08

    申请号:US11766583

    申请日:2007-06-21

    申请人: Yupin Fong Jun Wan

    发明人: Yupin Fong Jun Wan

    IPC分类号: G11C11/03

    摘要: To program a set of non-volatile storage elements, a set of programming pulses are applied to the control gates (or other terminals) of the non-volatile storage elements. The programming pulses have a constant pulse width and increasing magnitudes until a maximum voltage is reached. At that point, the magnitude of the programming pulses stops increasing and the programming pulses are applied in a manner to provide varying time duration of the programming signal between verification operations. For example, after the pulses reach the maximum magnitude the pulse widths are increased. Alternatively, after the pulses reach the maximum magnitude multiple program pulses are applied between verification operations.

    摘要翻译: 为了对一组非易失性存储元件进行编程,将一组编程脉冲施加到非易失性存储元件的控制门(或其它终端)。 编程脉冲具有恒定的脉冲宽度和增加的幅度,直到达到最大电压。 在这一点上,编程脉冲的幅度停止增加,编程脉冲以一种方式施加,以便在验证操作之间提供编程信号的变化的持续时间。 例如,在脉冲达到最大幅度之后,脉冲宽度增加。 或者,在脉冲达到最大幅度之后,在验证操作之间施加多个编程脉冲。