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    Aggregating data latches for program level determination
    2.
    发明授权
    Aggregating data latches for program level determination 有权
    汇总数据锁存器进行程序级确定

    公开(公告)号：US08737125B2

    公开(公告)日：2014-05-27

    申请号：US13569008

    申请日：2012-08-07

    申请人： Feng Pan ,  Tien-Chien Kuo ,  Jun Wan ,  Bo Lei

    发明人： Feng Pan ,  Tien-Chien Kuo ,  Jun Wan ,  Bo Lei

    IPC分类号： G11C16/04 ,  G11C11/56

    CPC分类号： G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/34

    摘要： In a nonvolatile memory array that stores randomized data, the program level—the number of states per cell stored in a population of memory cells—may be determined from the aggregated results of a single read step. A circuit for aggregating binary results of a read step includes parallel transistors with control gates connected to the data latches holding the binary results, so that current flow through the combined transistors depends on the binary results.

    摘要翻译： 在存储随机化数据的非易失性存储器阵列中，可以从单个读取步骤的聚合结果确定程序级 - 存储在存储器单元群中的每个存储单元的状态数。 用于聚合读取步骤的二进制结果的电路包括具有连接到保持二进制结果的数据锁存器的控制栅极的并行晶体管，使得通过组合晶体管的电流依赖于二进制结果。

    Data coding for improved ECC efficiency
    3.
    发明授权
    Data coding for improved ECC efficiency 有权
    数据编码，提高ECC效率

    公开(公告)号：US08473809B2

    公开(公告)日：2013-06-25

    申请号：US12839237

    申请日：2010-07-19

    申请人： Jun Wan ,  Alex Mak ,  Tien-Chien Kuo ,  Yan Li ,  Jian Chen

    发明人： Jun Wan ,  Alex Mak ,  Tien-Chien Kuo ,  Yan Li ,  Jian Chen

    IPC分类号： G06F11/00 ,  G11C29/00 ,  G11C7/00

    CPC分类号： G11C11/5642 ,  G11C11/5628 ,  G11C29/00

    摘要： Non-volatile storage devices and techniques for operating non-volatile storage are described herein. One embodiment includes accessing “n” pages of data to be programmed into a group of non-volatile storage elements. The “n” pages are mapped to a data state for each of the non-volatile storage elements based on a coding scheme that evenly distributes read errors across the “n” pages of data. Each of the non-volatile storage elements in the group are programmed to a threshold voltage range based on the data states to which the plurality of pages have been mapped. The programming may include programming the “n” pages simultaneously. In one embodiment, mapping the plurality of pages is based on a coding scheme that distributes a significant failure mode (for example, program disturb errors) to a first of the pages and a significant failure mode (for example, data retention errors) to a second of the pages.

    摘要翻译： 本文描述了用于操作非易失性存储器的非易失性存储设备和技术。 一个实施例包括访问要编程到一组非易失性存储元件中的“n”页数据。 基于在“n”页数据上均匀分布读取错误的编码方案，将“n”个页映射到每个非易失性存储元件的数据状态。 基于已经映射了多个页面的数据状态，组中的每个非易失性存储元件被编程到阈值电压范围。 编程可以包括同时对“n”页进行编程。 在一个实施例中，映射多个页面是基于将显着的故障模式（例如，程序干扰错误）分配给第一页面的编码方案和将重大故障模式（例如，数据保留错误）分配给 第二页。

    Corrugated settling cup and a multi-cup uniform flux gas anchor
    4.
    发明授权
    Corrugated settling cup and a multi-cup uniform flux gas anchor 有权
    波纹沉降杯和多杯均匀通量气锚

    公开(公告)号：US08453726B2

    公开(公告)日：2013-06-04

    申请号：US12673064

    申请日：2008-08-22

    申请人： Demin Wang ,  Yan Wang ,  Jun Wan ,  Shumin Zhang ,  Rongjie Zhu ,  Li Li

    发明人： Demin Wang ,  Yan Wang ,  Jun Wan ,  Shumin Zhang ,  Rongjie Zhu ,  Li Li

    IPC分类号： E21B43/38

    CPC分类号： E21B43/38 ,  E21B43/127 ,  F04B47/02

    摘要： A corrugated settling cup (5) is provided, wherein the cup has a cup body, an opening and a location step (52) are provided at the bottom (55) of the cup body, several location holes (53) are formed at the top of the location step (52), location projections (54) corresponding to the location holes (53) are formed at the bottom (55) of the corrugated settling cup (5), wherein the external profile of the corrugated settling cup body rises along the axial direction in a corrugated shape. A multi-cup uniform flux gas anchor is provided, wherein the gas anchor includes a central pipe (7), several corrugated settling cups (5), several settling cups protection bodies (6) and a well-flushing valve (9), wherein the external profile of the corrugated settling cup body rises along the axial direction in a corrugated shape.

    摘要翻译： 提供了一种波纹沉降杯（5），其中杯体具有杯体，在杯体的底部（55）设有开口和位置台阶（52），多个位置孔（53）形成在 在波纹沉降杯（5）的底部（55）形成位置台阶（52）的顶部，对应于定位孔（53）的定位突起（54），其中波纹沉降杯体的外部轮廓上升 沿轴向以波纹形状。 提供了一种多杯均匀的通量气体锚定器，其中气锚包括中心管（7），多个波纹沉降杯（5），多个沉降杯保护体（6）和井冲洗阀（9），其中 波纹沉降杯体的外部轮廓沿轴向方向以波纹形状上升。

    Detection of broken word-lines in memory arrays
    5.
    发明授权
    Detection of broken word-lines in memory arrays 有权
    检测存储器阵列中断字符

    公开(公告)号：US08379454B2

    公开(公告)日：2013-02-19

    申请号：US13101765

    申请日：2011-05-05

    申请人： Mrinal Kochar ,  Jianmin Huang ,  Jun Wan

    发明人： Mrinal Kochar ,  Jianmin Huang ,  Jun Wan

    IPC分类号： G11C16/04

    CPC分类号： G11C29/52 ,  G11C16/3418 ,  G11C16/3459 ,  G11C29/025

    摘要： Techniques and corresponding circuitry are presented for the detection of broken wordlines in a memory array. An “inter-word-line” comparison where the program loop counts of different word-lines are compared in order to determine whether a word-line may be defective. The number of programming pulses needed for the cells along a word-line WLn is compared to the number needed for a preceding word-line, such as WLn or WL(n−1), to see whether it exceeds this earlier value by a threshold value. If the word-line requires an excessive number of pulses, relative the earlier word-line, to complete programming, it is treated as defective.

    摘要翻译： 提供技术和相应的电路用于检测存储器阵列中的断字。 比较不同字线的程序循环计数的字间对比比较，以确定字线是否有缺陷。 将沿着字线WLn的单元所需的编程脉冲的数量与前一字线（例如WLn或WL（n-1））所需的数字进行比较，以查看其是否超过该较早的值一个阈值 值。 如果字线需要过多的脉冲数，相对于较早的字线，要完成编程，则将其视为有缺陷的。

    Dual bit line metal layers for non-volatile memory
    6.
    发明授权
    Dual bit line metal layers for non-volatile memory 有权
    用于非易失性存储器的双位线金属层

    公开(公告)号：US08368137B2

    公开(公告)日：2013-02-05

    申请号：US11768468

    申请日：2007-06-26

    申请人： Nima Mokhlesi ,  Jun Wan

    发明人： Nima Mokhlesi ,  Jun Wan

    IPC分类号： H01L29/788

    CPC分类号： G11C5/063 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/18 ,  G11C16/0483 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

    摘要： Structures and techniques are disclosed for reducing bit line to bit line capacitance in a non-volatile storage system. The bit lines are formed at a 4ƒpitch in each of two separate metal layers, and arranged to alternate between each of the layers. In an alternative embodiment, shields are formed between each of the bit lines on each metal layer.

    摘要翻译： 公开了用于在非易失性存储系统中减少位线到位线电容的结构和技术。 位线在两个分离的金属层中的每一个中以4fpitch形成，并且布置成在每个层之间交替。 在替代实施例中，在每个金属层上的每个位线之间形成屏蔽。

    Detection of Broken Word-Lines in Memory Arrays
    7.
    发明申请
    Detection of Broken Word-Lines in Memory Arrays 有权
    在内存数组中检测破碎的字线

    公开(公告)号：US20120281479A1

    公开(公告)日：2012-11-08

    申请号：US13101765

    申请日：2011-05-05

    申请人： Mrinal Kochar ,  Jianmin Huang ,  Jun Wan

    发明人： Mrinal Kochar ,  Jianmin Huang ,  Jun Wan

    IPC分类号： G11C16/10

    CPC分类号： G11C29/52 ,  G11C16/3418 ,  G11C16/3459 ,  G11C29/025

    摘要： Techniques and corresponding circuitry are presented for the detection of broken wordlines in a memory array. One example considers an “inter-word-line” comparison where the program loop counts of different word-lines are compared in order to determine whether a word-line may be defective. For example, the number of programming pulses needed for the cells along a word-line WLn is compared to the number needed for a preceding word-line, such as WLn or WL(n−1), to see whether it exceeds this earlier value by a threshold value. If the word-line requires an excessive number of pulses, relative the earlier word-line, to complete programming, it is treated as defective.

    摘要翻译： 提供技术和相应的电路用于检测存储器阵列中的断字。 一个例子考虑比较不同字线的程序循环计数以便确定字线是否有缺陷的字间对比比较。 例如，将沿着字线WLn的单元所需的编程脉冲的数量与先前的字线（例如WLn或WL（n-1））所需的数字进行比较，以查看其是否超过该较早的值 通过阈值。 如果字线需要过多的脉冲数，相对于较早的字线，要完成编程，则将其视为有缺陷的。

    INTELLIGENT CONTROL OF PROGRAM PULSE FOR NON-VOLATILE STORAGE
    8.
    发明申请
    INTELLIGENT CONTROL OF PROGRAM PULSE FOR NON-VOLATILE STORAGE 有权
    智能控制非挥发性存储的程序脉冲

    公开(公告)号：US20100046301A1

    公开(公告)日：2010-02-25

    申请号：US12607329

    申请日：2009-10-28

    申请人： Yupin Fong ,  Jun Wan

    发明人： Yupin Fong ,  Jun Wan

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

    摘要： To program a set of non-volatile storage elements, a set of programming pulses are applied to the control gates (or other terminals) of the non-volatile storage elements. The programming pulses have a constant pulse width and increasing magnitudes until a maximum voltage is reached. At that point, the magnitude of the programming pulses stops increasing and the programming pulses are applied in a manner to provide varying time duration of the programming signal between verification operations. In one embodiment, for example, after the pulses reach the maximum magnitude the pulse widths are increased. In another embodiment, after the pulses reach the maximum magnitude multiple program pulses are applied between verification operations.

    摘要翻译： 为了对一组非易失性存储元件进行编程，将一组编程脉冲施加到非易失性存储元件的控制门（或其它终端）。 编程脉冲具有恒定的脉冲宽度和增加的幅度，直到达到最大电压。 在这一点上，编程脉冲的幅度停止增加，编程脉冲以一种方式施加，以便在验证操作之间提供编程信号的变化的持续时间。 在一个实施例中，例如，在脉冲达到最大幅度之后，脉冲宽度增加。 在另一个实施例中，在脉冲达到最大幅度之后，在验证操作之间施加多个编程脉冲。

    Retention margin program verification
    9.
    发明授权
    Retention margin program verification 有权
    保留保证金计划验证

    公开(公告)号：US07616499B2

    公开(公告)日：2009-11-10

    申请号：US11617541

    申请日：2006-12-28

    申请人： Jun Wan ,  Jeffrey W. Lutze ,  Jian Chen ,  Yan Li ,  Alex Mak

    发明人： Jun Wan ,  Jeffrey W. Lutze ,  Jian Chen ,  Yan Li ,  Alex Mak

    IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/06

    CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

    摘要： Data verification in a memory device using a portion of a data retention margin is provided. A bit count is read from the region to determine whether errors will result in the memory. A read in one or more retention margin portions is performed after the normal program verify sequence and if the number of bits in these regions is more than a pre-set the memory will fail verify status. A method of verifying data in a memory device includes the steps of: defining an retention margin between adjacent data thresholds; programming the memory device with data; determining whether bits are present in the data retention margin; and if the number of bits in the retention margin exceeds a threshold, generating an error.

    摘要翻译： 提供了使用部分数据保留余量的存储器件中的数据验证。 从区域读取位计数，以确定错误是否会导致内存。 在正常程序验证序列之后执行在一个或多个保留边缘部分中的读取，并且如果这些区域中的位数大于预设，则存储器将失败验证状态。 验证存储器件中的数据的方法包括以下步骤：定义相邻数据阈值之间的保留余量; 使用数据对存储设备进行编程; 确定位是否存在于数据保留余量中; 并且如果保留余量中的比特数超过阈值，则产生错误。

    RFID temperature logger incorporating a frequency ratio digitizing temperature sensor
    10.
    发明授权
    RFID temperature logger incorporating a frequency ratio digitizing temperature sensor 有权
    RFID温度记录仪采用频率比数字化温度传感器

    公开(公告)号：US07474230B2

    公开(公告)日：2009-01-06

    申请号：US11425381

    申请日：2006-06-20

    申请人： Eric D. Blom ,  Jun Wan ,  Stuart H. Urie

    发明人： Eric D. Blom ,  Jun Wan ,  Stuart H. Urie

    IPC分类号： G08C17/00

    CPC分类号： G01K7/01

    摘要： A semi-passive radio frequency identification (RFID) tag being coupled to a battery providing a battery voltage for powering a part of the circuitry of the RFID tag includes an RF communication block receiving and transmitting RF signals, a sensor block including a frequency ratio digitizing temperature sensor for alternately measuring the ambient temperature and the battery voltage, and a control logic block in communication with the RF communication block and the sensor block. The control logic controls the operation of the RF communication block and the sensor block and stores temperature and voltage measurement data generated by the sensor block. In one embodiment, the control logic block of the RFID tag operates based on a system clock and the sensor block provides a reference clock to the control logic block for use in calibrating the system clock of the control logic block.

    摘要翻译： 耦合到提供用于为RFID标签的电路的一部分供电的电池电压的电池的半无源射频识别（RFID）标签包括接收和发送RF信号的RF通信块，包括频率比数字化的传感器块 用于交替测量环境温度和电池电压的温度传感器，以及与RF通信块和传感器块通信的控制逻辑块。 控制逻辑控制RF通信块和传感器块的操作，并存储由传感器块产生的温度和电压测量数据。 在一个实施例中，RFID标签的控制逻辑块基于系统时钟进行操作，并且传感器块向控制逻辑块提供参考时钟以用于校准控制逻辑块的系统时钟。