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61.发明授权Scatterometry techniques to ascertain asymmetry profile of features and generate a feedback or feedforward process control data associated therewith 有权散射技术来确定特征的不对称轮廓，并产生与之相关联的反馈或前馈过程控制数据公开(公告)号：US06650422B2
公开(公告)日：2003-11-18
申请号：US09817820
申请日：2001-03-26
IPC分类号： G01B1100
CPC分类号： G01B11/30 , G01B11/24 , G01B11/26 , G01N21/211 , G01N21/4738 , G01N21/9501
摘要： The present invention is directed to a method and a system for non-destructively, efficiently and accurately detecting asymmetry in the profile of a feature formed on a wafer during the process of semiconductor fabrication. The method encompasses directing a beam of light or radiation at a feature and detecting a reflected beam associated therewith. Data associated with the reflected beam is correlated with data associated with known feature profiles to ascertain profile characteristics associated with the feature of interest. Using the profile characteristics, an asymmetry of the feature is determined which is then used to generate feedback or feedforward process control data to compensate for or correct such asymmetry in subsequent processing.
摘要翻译： 本发明涉及一种用于在半导体制造过程中非破坏性地，有效地和准确地检测在晶片上形成的特征的轮廓的不对称性的方法和系统。 该方法包括在特征处引导光束或辐射，并且检测与其相关联的反射光束。 与反射光束相关联的数据与与已知特征轮廓相关联的数据相关联，以确定与感兴趣特征相关联的轮廓特征。 使用简档特征，确定特征的不对称性，然后将其用于产生反馈或前馈过程控制数据，以补偿或纠正随后处理中的这种不对称性。
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公开(公告)号：US06645702B1
公开(公告)日：2003-11-11
申请号：US10050438
申请日：2002-01-16
IPC分类号： G03F700
CPC分类号： G03F7/265 , H01L21/0273 , H01L21/31144 , H01L21/32139
摘要： The present invention relates to systems and methods for increasing the hydrophobicity of patterned resists. In one embodiment, the present invention relates to a method of processing an ultra-thin resist, involving depositing the ultra-thin photoresist over a semiconductor substrate; irradiating the ultra-thin resist with electromagnetic radiation; developing the ultra-thin resist with a developer to form a patterned resist, the patterned resist having a surface with a first hydrophobicity; contacting the patterned resist with a transition solvent to provide the surface of the patterned resist with a second hydrophobicity, wherein the second hydrophobicity is greater than the first hydrophobicity and contact of the patterned resist with the transition is conducted between developing the ultra-thin resist and rinsing patterned resist; and rinsing the patterned resist having the second hydrophobicity with an aqueous solution.
摘要翻译： 本发明涉及增加图案化抗蚀剂疏水性的系统和方法。 在一个实施例中，本发明涉及一种处理超薄抗蚀剂的方法，包括在半导体衬底上沉积超薄光致抗蚀剂; 用电磁辐射照射超薄抗蚀剂; 用显影剂显影超薄抗蚀剂以形成图案化抗蚀剂，图案化抗蚀剂具有第一疏水性表面; 使图案化的抗蚀剂与过渡溶剂接触以提供具有第二疏水性的图案化抗蚀剂的表面，其中第二疏水性大于第一疏水性，并且图案化的抗蚀剂与转变的接触在显影超薄抗蚀剂和 冲洗图案抗蚀剂; 并用水溶液冲洗具有第二疏水性的图案化抗蚀剂。
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公开(公告)号：US06593210B1
公开(公告)日：2003-07-15
申请号：US09707214
申请日：2000-11-06
IPC分类号： H01L2176
CPC分类号： H01L21/76229 , H01L21/31053 , H01L21/31055 , H01L21/31058
摘要： One aspect of the present invention relates to a method of forming trench isolation regions within a semiconductor substrate, involving the steps of forming trenches in the semiconductor substrate; depositing a semi-conformal dielectric material over the substrate, wherein the semi-conformal dielectric material has valleys positioned over the trenches; forming an inorganic conformal film over the semi-conformal dielectric material; polishing the semiconductor substrate whereby a first portion of the inorganic conformal film is removed thereby exposing a portion of the semi-conformal dielectric material, and a second portion remains over the valleys of the semi-conformal dielectric material; removing the exposed portions of the semi-conformal dielectric material; and planarizing the substrate to provide the semiconductor substrate having trenches with a dielectric material therein.
摘要翻译： 本发明的一个方面涉及一种在半导体衬底内形成沟槽隔离区域的方法，包括在半导体衬底中形成沟槽的步骤; 在所述衬底上沉积半保形介电材料，其中所述半保形介电材料具有位于所述沟槽上方的谷; 在半保形介电材料上形成无机保形膜; 抛光所述半导体衬底，由此去除所述无机保形膜的第一部分，从而暴露所述半共形绝缘材料的一部分，并且第二部分保留在所述半共形绝缘材料的所述谷的上方; 去除所述半共形介电材料的暴露部分; 并且平坦化衬底以提供其中具有介电材料的沟槽的半导体衬底。
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公开(公告)号：US06592932B2
公开(公告)日：2003-07-15
申请号：US09814131
申请日：2001-03-21
申请人： Ramkumar Subramanian , Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh , Michael K. Templeton , Sanjay K. Yedur
发明人： Ramkumar Subramanian , Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh , Michael K. Templeton , Sanjay K. Yedur
IPC分类号： B05D312
CPC分类号： H01L21/6715 , G03F7/3021
摘要： A system and method is provided that facilitates the application of a uniform layer of developer material on a photoresist material layer. The system includes a nozzle adapted to apply a predetermined volume of developer material on a photoresist material layer along a linear path having a length approximately equal to the diameter of the photoresist material layer. A movement system moves the nozzle to a first position offset from a central region of the photoresist material layer for applying a first predetermined volume of developer material to the photoresist material layer while the developer material is spin coated. The movement system also moves the nozzle to a second position offset from the central region for applying a second predetermined volume of developer material to the photoresist material layer while the developer is spin coated. The first position is located on an opposite side of the central region with respect to the second position. A method of adjusting the offset position and/or volume of developer material applied at the first and second position is also provided. The method utilizes developed photoresist material layer thickness data provided by a measurement system to adjust the offset position and/or volume of the developer.
摘要翻译： 提供了一种有助于在光致抗蚀剂材料层上施加均匀的显影剂材料层的系统和方法。 该系统包括适于沿着具有大致等于光致抗蚀剂材料层的直径的直线路径的光致抗蚀剂材料层上施加预定体积的显影剂材料的喷嘴。 移动系统将喷嘴移动到偏离光致抗蚀剂材料层的中心区域的第一位置，以在旋转涂覆显影剂材料的同时将第一预定体积的显影剂材料施加到光致抗蚀剂材料层。 移动系统还将喷嘴移动到偏离中心区域的第二位置，以在旋涂涂覆显影剂的同时将第二预定体积的显影剂材料施加到光致抗蚀剂材料层。 第一位置相对于第二位置位于中心区域的相反侧。 还提供了一种调节在第一和第二位置施加的显影剂材料的偏移位置和/或体积的方法。 该方法利用由测量系统提供的显影的光致抗蚀剂材料层厚度数据来调节显影剂的偏移位置和/或体积。
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公开(公告)号：US06579733B1
公开(公告)日：2003-06-17
申请号：US10196407
申请日：2002-07-16
IPC分类号： H01L2166
CPC分类号： H01L22/12
摘要： The present invention provides systems and methods wherein scatterometry is used to control an implant processes, such as an angled implant process. According to the invention, data relating to resist dimensions is obtained by scatterometry prior to an the implant process. The data is used to determine whether a resist is suitable for an implant process and/or determine an appropriate condition, such as an angle of implant or implantation dose, for an implant process.
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公开(公告)号：US06561706B2
公开(公告)日：2003-05-13
申请号：US09893807
申请日：2001-06-28
IPC分类号： G03D500
CPC分类号： G03F7/70633 , G03F7/70675
摘要： A system for monitoring a latent image exposed in a photo resist during semiconductor manufacture is provided. The system includes one or more light sources, each light source directing light to the latent image and/or one or more gratings exposed on one or more portions of a wafer. Light reflected from the latent image and/or the gratings is collected by a signature system, which processes the collected light. Light passing through the latent image and/or gratings may similarly be collected by the signature system, which processes the collected light. The collected light is analyzed and can be employed to generate feedback information to control the exposure. The collect light is further analyzed and can be employed to generate feed forward information that can be employed to control post exposure processes including development and baking processes.
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公开(公告)号：US06535288B1
公开(公告)日：2003-03-18
申请号：US09902351
申请日：2001-07-10
IPC分类号： G01N2189
CPC分类号： H01L21/67253 , C23C14/547 , C23C16/52 , G01N21/47 , G01N21/9501 , H01L22/26
摘要： The present invention is directed to a system and a method for controlling a thin film formation on a moving substrate as part of a process for manufacturing an integrated circuit. The invention involves the use of scatterometry to control the thin film formation process by analyzing the thin film on the moving substrate comprising an optical indicia and a periodic analysis structure in a periodic manner. The optical indicia is spatially associated with the periodic analysis structure and is utilized in conjunction with a signaling system to determine a position of the moving substrate, whereby a repeatable analysis of a corresponding location on the moving substrate can be performed. Scatterometry permits in-situ measurements of thin film formation progress, whereby thin film formation process conditions can be controlled in a feedback loop to obtain a targeted result. Scatterometry can also be facilitated by providing a grating pattern on a non-production portion of the substrate.
摘要翻译： 本发明涉及一种用于控制移动衬底上的薄膜形成的系统和方法，作为用于制造集成电路的工艺的一部分。 本发明涉及使用散射法来通过以周期性方式分析包括光学标记和周期性分析结构的移动衬底上的薄膜来控制薄膜形成过程。 光学标记在空间上与周期性分析结构相关联，并且与信号系统结合使用以确定移动的衬底的位置，由此可以执行移动衬底上相应位置的可重复分析。 散射测量允许原位测量薄膜形成进程，由此可以在反馈回路中控制薄膜形成工艺条件以获得目标结果。 也可以通过在基板的非生产部分上提供光栅图案来促进散射测量。
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68.发明授权公开(公告)号：US06501534B1
公开(公告)日：2002-12-31
申请号：US09845375
申请日：2001-04-30
IPC分类号： G03B2752
CPC分类号： G03F7/70516 , G03F7/70558 , G03F7/70625 , G03F7/70641
摘要： The present invention is directed to a system and a method for calibrating a lithography stepper system. The system includes a lithography stepper system, measurement system such as a scatterometry system, and a processor for correlating an ideal “golden standard” characterization signature to a test structure characterization data set, based on a plurality of focus and exposure conditions.
摘要翻译： 本发明涉及用于校准光刻步进系统的系统和方法。 该系统包括光刻步进系统，诸如散射测量系统的测量系统和用于基于多个焦点和曝光条件将理想“黄金标准”表征特征与测试结构表征数据集相关联的处理器。
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公开(公告)号：US06465156B1
公开(公告)日：2002-10-15
申请号：US09422390
申请日：1999-10-21
IPC分类号： G03F738
摘要： The present invention relates to a method for mitigating formation of silicon grass. A silylation process is performed on a semiconductor structure, the structure including a photoresist layer, an underlayer under the photoresist layer, and a substrate under the underlayer. A chemical mechanical polishing process is employed to remove a portion of the photoresist layer.
摘要翻译： 本发明涉及减轻硅草的形成的方法。 在半导体结构上进行甲硅烷化处理，该结构包括光致抗蚀剂层，光致抗蚀剂层下的底层和底层下的基底。 采用化学机械抛光工艺去除一部分光致抗蚀剂层。
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70.发明授权System and method for facilitating determining suitable material layer thickness in a semiconductor device fabrication process 失效用于在半导体器件制造工艺中有助于确定合适的材料层厚度的系统和方法公开(公告)号：US06459945B1
公开(公告)日：2002-10-01
申请号：US09311223
申请日：1999-05-13
IPC分类号： G06F1900
CPC分类号： B24B37/013 , B24B49/04 , H01L21/67253 , H01L22/34
摘要： The present invention relates to a test wafer for use in optimizing a process. The test wafer includes a substrate and a material layer formed over the substrate, wherein the material layer includes N number of test regions (N being an integer greater than one). At least one of the test regions has a material layer thickness different from another of the test regions. A spindle drive system is also provided for driving at least one spindle. One end of the at least one spindle is coupled to a polishing pad, which is employed in forming the test regions.
摘要翻译： 本发明涉及用于优化工艺的测试晶片。 测试晶片包括衬底和形成在衬底上的材料层，其中材料层包括N个测试区域（N是大于1的整数）。 测试区域中的至少一个具有与另一个测试区域不同的材料层厚度。 还提供用于驱动至少一个主轴的主轴驱动系统。 所述至少一个心轴的一端连接到用于形成所述测试区域的抛光垫。
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