公开(公告)号：US08183647B2

公开(公告)日：2012-05-22

申请号：US10732511

申请日：2003-12-11

申请人： Tadahiro Omi ,  Naoki Ueda

发明人： Tadahiro Omi ,  Naoki Ueda

IPC分类号： H01L29/76

CPC分类号： H01L21/28202 ,  H01L29/42368 ,  H01L29/518 ,  H01L29/66666 ,  H01L29/7827

摘要： The present invention provides a semiconductor device comprising: a silicon based semiconductor substrate provided with a step including an non-horizontal surface, a horizontal surface and a connection region for connecting the non-horizontal surface and the horizontal surface; a gate insulating film formed in at least a part of the step; and a gate electrode formed on the gate insulating film, wherein the entirety or a part of the gate insulating film is formed of a silicon oxynitride film that contains a rare gas element at a area density of 1010 cm−2 or more in at least a part of the silicon oxynitride film.

摘要翻译： 本发明提供一种半导体器件，包括：硅基半导体衬底，设置有包括用于连接非水平表面和水平表面的非水平表面，水平表面和连接区域的步骤; 形成在所述台阶的至少一部分上的栅极绝缘膜; 以及形成在所述栅极绝缘膜上的栅电极，其中，所述栅极绝缘膜的整体或一部分由至少含有所述绝缘膜的区域密度为1010cm -2以上的稀有气体元素的氮氧化硅膜形成 氧氮化硅膜的一部分。

公开(公告)号：US07612397B2

公开(公告)日：2009-11-03

申请号：US11938568

申请日：2007-11-12

申请人： Naoki Ueda ,  Yoshimitsu Yamauchi

发明人： Naoki Ueda ,  Yoshimitsu Yamauchi

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119 ,  H01L29/00

CPC分类号： G11C16/10 ,  G11C8/10 ,  G11C2216/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11558

摘要： A nonvolatile memory cell that can be mounted in a CMOS manufacturing process, and is capable of implementing high level of programming, reading and erasing ability. The memory cell is configured by a MOS transistor including two N-type first impurity diffusion layers formed separately on a P-type semiconductor substrate, and a first gate electrode formed above a first cannel region sandwiched by both diffusion layers through a first gate insulation film, a first capacitor comprising P-type second impurity diffusion layers formed on a well, and a second gate electrode formed above the diffusion layer through a second gate insulation film, and a second capacitor comprising the well adjacent to the second impurity diffusion layer, and a third gate electrode formed above the well through a third gate insulation film, wherein a different voltage can be applied to each of the capacitors.

摘要翻译： 可以安装在CMOS制造工艺中的非易失性存储单元，并且能够实现高水平的编程，读取和擦除能力。 存储单元由包括在P型半导体衬底上分别形成的两个N型第一杂质扩散层的MOS晶体管构成，第一栅极形成在通过第一栅极绝缘膜被两个扩散层夹持的第一沟道区域上方 包括形成在阱上的P型第二杂质扩散层的第一电容器和通过第二栅极绝缘膜形成在扩散层上方的第二栅电极，以及包括与第二杂质扩散层相邻的阱的第二电容器，以及 通过第三栅极绝缘膜在阱上方形成的第三栅电极，其中可以向每个电容器施加不同的电压。

公开(公告)号：US07515480B2

公开(公告)日：2009-04-07

申请号：US11592043

申请日：2006-11-01

申请人： Masahiro Tomida ,  Naoki Ueda

发明人： Masahiro Tomida ,  Naoki Ueda

IPC分类号： G11C11/34

CPC分类号： G11C8/08 ,  G11C7/22 ,  G11C16/10

摘要： A nonvolatile semiconductor memory device and its writing method for reducing a writing rate variation without changing a voltage condition applied for each memory cell in writing operation is provided. The device comprises a memory cell array configuration where each drain of the memory cells on the same column is connected to a first bit line via a second bit line and a bit line contact, and the shortest distance from each drain of the memory cells to the bit line contact varies according to a location of the memory cell in the column direction. The method includes a writing operation carried out sequentially from the nearest memory cell to the bit line contact, upon writing continuously so that the memory cell current becomes small for all or some of the memory cells on the same column between the two adjacent bit line contacts in the column direction.

摘要翻译： 提供了一种非易失性半导体存储器件及其写入方法，用于在不改变在写入操作中对每个存储单元施加的电压条件的同时降低写入速率变化。 该器件包括存储单元阵列配置，其中同一列上的存储器单元的每个漏极经由第二位线和位线接触连接到第一位线，以及从存储器单元的每个漏极到第一位线的最短距离 位线接触根据存储单元在列方向上的位置而变化。 该方法包括在连续写入时从最近的存储单元顺序执行的写入操作，使得存储单元电流对于两个相邻位线触点之间的同一列上的所有或一些存储单元的电流变小 在列方向。

公开(公告)号：US20090046514A1

公开(公告)日：2009-02-19

申请号：US12094379

申请日：2006-11-01

申请人： Kaoru Yamamoto ,  Nobuhiko Ito ,  Naoki Ueda ,  Yoshimitsu Yamauchi

发明人： Kaoru Yamamoto ,  Nobuhiko Ito ,  Naoki Ueda ,  Yoshimitsu Yamauchi

IPC分类号： G11C11/34

CPC分类号： G11C16/0491 ,  G11C16/24 ,  G11C16/26

摘要： A virtual ground type semiconductor memory device comprises: a memory cell array in which nonvolatile memory cells each including a first electrode, a pair of second electrodes, and a charge retention part are arranged in row and column directions like a matrix; a read circuit for selecting a pair of the first and second bit lines connected to a selected memory cell to be read, applying first and second read voltages to the selected first and second bit lines, respectively, and detecting a magnitude of a memory cell current flowing in the selected memory cell, at the time of reading; a voltage applying means for applying the second read voltage to a second adjacent bit line adjacent to the selected second bit line on the opposite side of the first bit line; and a short-circuit means for short-circuiting the selected second bit line and the second adjacent bit line.

摘要翻译： 虚拟接地型半导体存储器件包括：存储单元阵列，其中包括第一电极，一对第二电极和电荷保持部分的非易失性存储单元排列成像矩阵的行和列方向; 读取电路，用于选择连接到要读取的所选择的存储器单元的一对第一和第二位线，将第一和第二读取电压分别施加到所选择的第一和第二位线，并且检测存储单元电流的大小 在读取时流入所选存储单元; 电压施加装置，用于将第二读取电压施加到与第一位线的相对侧上的所选择的第二位线相邻的第二相邻位线; 以及用于短路所选择的第二位线和第二相邻位线的短路装置。

公开(公告)号：US07283391B2

公开(公告)日：2007-10-16

申请号：US10934212

申请日：2004-09-03

申请人： Naoki Ueda ,  Nobuhiko Ito ,  Yoshimitsu Yamauchi

发明人： Naoki Ueda ,  Nobuhiko Ito ,  Yoshimitsu Yamauchi

IPC分类号： G11C16/04 ,  G11C5/14 ,  G11C7/00

CPC分类号： G11C16/24

摘要： A semiconductor memory device comprises: a plurality of memory elements; at least one bit line, wherein a memory operation is performed via at least a portion of the bit line with respect to at least one of the plurality of memory elements; and a load resistance regulating circuit for changing a resistance value to reduce or eliminate a difference in bit line load resistance depending on a position of the memory element.

摘要翻译： 半导体存储器件包括：多个存储元件; 至少一个位线，其中通过所述位线的至少一部分相对于所述多个存储器元件中的至少一个执行存储器操作; 以及负载电阻调节电路，用于根据存储元件的位置改变电阻值以减少或消除位线负载电阻的差异。

公开(公告)号：US07210520B2

公开(公告)日：2007-05-01

申请号：US11060603

申请日：2005-02-17

申请人： Yasutoshi Yamanaka ,  Haruhiko Watanabe ,  Naoki Ueda

发明人： Yasutoshi Yamanaka ,  Haruhiko Watanabe ,  Naoki Ueda

IPC分类号： F28F9/02

CPC分类号： F28F9/0224 ,  F28D2021/0082 ,  F28F9/02 ,  F28F9/0229 ,  F28F2009/029 ,  F28F2225/08

摘要： A heat exchanger according to the present invention has a plurality of tubes, header tanks and a support. Fluid flows through the plurality of tubes. The header tanks have a core plate and a tank body, and are disposed at longitudinal end portions of the plurality of tubes in such a manner to be communicated with internal spaces of the plurality of tubes. The core plate has approximately arc-shaped cross-section of which both side fringes are fixed onto the tank body and of which a middle portion fixes the longitudinal end portions of the plurality of tubes therein and bulges with respect to the both side fringes toward the plurality of tubes. The tank body and the core plate form an internal space of each of the header tanks. The support retains an interval between the both side fringes.

摘要翻译： 根据本发明的热交换器具有多个管，集水箱和支撑件。 流体流过多个管。 集水箱具有芯板和罐体，并且以与多个管的内部空间连通的方式设置在多个管的纵向端部。 芯板具有大致弧形的横截面，其两侧边缘固定在罐体上，其中间部分将多个管的纵向端部固定在其中，相对于两侧边缘朝向 多个管。 罐体和芯板形成每个集水箱的内部空间。 支撑件保持两边条纹之间的间隔。

公开(公告)号：US20060086491A1

公开(公告)日：2006-04-27

申请号：US11257466

申请日：2005-10-24

申请人： Naoki Ueda

发明人： Naoki Ueda

IPC分类号： F28F1/40 ,  B21D21/00

CPC分类号： F28D1/0391 ,  B21D53/02 ,  B23K1/0012 ,  B23K26/244 ,  B23K2101/02 ,  B23K2101/06 ,  B23K2101/08 ,  B23K2101/14 ,  B23P15/26 ,  F28F3/025 ,  Y10T29/49391

摘要： A heat exchanger includes at least one tube provided with an inner fin in a fluid passage which is defined by the tube therein and has a substantially ellipse-shaped cross section. A plate member for constructing the tube has two edge portions, which overlap each other and are integrally joined at a single joint disposed at a major-axis direction end of the tube. The inner fin is arranged in the tube before the forming of the joint, thus improving an arrangement performance of the inner fin. Moreover, there exists the single joint positioned at the one end of the tube so that a joint reliability of the tube is enhanced.

摘要翻译： 一种热交换器包括至少一个管，该管在流体通道中设置有内翅片，所述流体通道由其中的管限定，并且具有大致椭圆形的横截面。 用于构造管的板构件具有两个彼此重叠的边缘部分，并且在设置在管的长轴方向端的单个接头处一体地接合。 在形成接头之前，内翅片配置在管内，从而提高了内翅片的排列性能。 此外，存在位于管的一端的单个接头，使得管的接合可靠性增强。

公开(公告)号：US07002204B2

公开(公告)日：2006-02-21

申请号：US10315222

申请日：2002-12-10

申请人： Naoki Ueda ,  Yasuhiro Sugita ,  Yoshimitsu Yamauchi

发明人： Naoki Ueda ,  Yasuhiro Sugita ,  Yoshimitsu Yamauchi

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/66825

摘要： A non-volatile semiconductor memory including at least one first gate electrode as a floating gate on a semiconductor substrate with intervention of a first insulating film as a tunnel oxide film; sidewall spacers on both sidewalls of the first gate electrode in a direction of a channel length; a bit line formed of an impurity diffusion region of a conductivity type different from the conductivity type of the semiconductor substrate in a surface layer of the semiconductor substrate by the side of the first gate electrode, wherein the bit line comprises a first bit line formed in self-alignment using the first gate electrode as a mask and a second bit line formed in self-alignment using the first gate electrode and the sidewall spacers as a mask.

公开(公告)号：US20050057993A1

公开(公告)日：2005-03-17

申请号：US10934212

申请日：2004-09-03

申请人： Naoki Ueda ,  Nobuhiko Ito ,  Yoshimitsu Yamauchi

发明人： Naoki Ueda ,  Nobuhiko Ito ,  Yoshimitsu Yamauchi

IPC分类号： G11C16/06 ,  G11C7/12 ,  G11C16/24 ,  G11C11/00

CPC分类号： G11C16/24

摘要： A semiconductor memory device comprises: a plurality of memory elements; at least one bit line, wherein a memory operation is performed via at least a portion of the bit line with respect to at least one of the plurality of memory elements; and a load resistance regulating circuit for changing a resistance value to reduce or eliminate a difference in bit line load resistance depending on a position of the memory element.

摘要翻译： 半导体存储器件包括：多个存储元件; 至少一个位线，其中通过所述位线的至少一部分相对于所述多个存储器元件中的至少一个执行存储器操作; 以及负载电阻调节电路，用于根据存储元件的位置改变电阻值以减少或消除位线负载电阻的差异。

公开(公告)号：US06323107B1

公开(公告)日：2001-11-27

申请号：US09547105

申请日：2000-04-11

申请人： Naoki Ueda ,  Masayuki Hirata ,  Shinichi Sato

发明人： Naoki Ueda ,  Masayuki Hirata ,  Shinichi Sato

IPC分类号： H01L2176

CPC分类号： H01L21/76235

摘要： A process for forming a device isolation region comprising the steps of: forming a pad oxide film and a silicon nitride film on a semiconductor substrate; removing the pad oxide film and the silicon nitride film on a region for device isolation and forming a trench in the semiconductor substrate by etching using the remaining pad oxide film and silicon nitride film as an etching mask; forming a first oxide film at least on the bottom and sidewalls of the trench and below the pad oxide film under an end portion of the silicon nitride film using the silicon nitride film as a mask resistant to oxidization; forming a gap between the silicon nitride film and the semiconductor substrate by removing the first oxide film on the bottom and the sidewalls of the trench and the first oxide film and the pad oxide film below the end portion of the silicon nitride film by etching using the silicon nitride film as an etching mask; forming a second oxide film at least on the bottom and the sidewalls of the trench and in the gap using the silicon nitride film as a mask resistant to oxidization; and forming a third oxide film so as to fill the trench, thereby to form a device isolation region.

摘要翻译： 一种用于形成器件隔离区的方法，包括以下步骤：在半导体衬底上形成衬垫氧化膜和氮化硅膜; 在用于器件隔离的区域上去除衬垫氧化膜和氮化硅膜，并通过使用剩余的衬垫氧化物膜和氮化硅膜作为蚀刻掩模通过蚀刻在半导体衬底中形成沟槽; 使用氮化硅膜作为耐氧化的掩模，在氮化硅膜的端部至少在沟槽的底部和侧壁上形成第一氧化物膜，并在衬垫氧化膜的下方形成第一氧化物膜; 通过在氮化硅膜的端部的下方除去沟槽的第一氧化膜和第一氧化膜和氧化铝膜的第一氧化膜，通过使用 氮化硅膜作为蚀刻掩模; 使用氮化硅膜作为耐氧化的掩模，至少在沟槽的底部和侧壁上以及在间隙中形成第二氧化物膜; 以及形成第三氧化物膜以填充沟槽，从而形成器件隔离区域。