公开(公告)号：US20070097724A1

公开(公告)日：2007-05-03

申请号：US11592043

申请日：2006-11-01

申请人： Masahiro Tomida ,  Naoki Ueda

发明人： Masahiro Tomida ,  Naoki Ueda

IPC分类号： G11C5/06

CPC分类号： G11C8/08 ,  G11C7/22 ,  G11C16/10

摘要： A nonvolatile semiconductor memory device and its writing method for reducing a writing rate variation without changing a voltage condition applied for each memory cell in writing operation is provided. The device comprises a memory cell array configuration where each drain of the memory cells on the same column is connected to a first bit line via a second bit line and a bit line contact, and the shortest distance from each drain of the memory cells to the bit line contact varies according to a location of the memory cell in the column direction. The method includes a writing operation carried out sequentially from the nearest memory cell to the bit line contact, upon writing continuously so that the memory cell current becomes small for all or some of the memory cells on the same column between the two adjacent bit line contacts in the column direction.

摘要翻译： 提供了一种非易失性半导体存储器件及其写入方法，用于在不改变在写入操作中对每个存储单元施加的电压条件的同时降低写入速率变化。 该器件包括存储单元阵列配置，其中同一列上的存储器单元的每个漏极经由第二位线和位线接触连接到第一位线，以及从存储器单元的每个漏极到第一位线的最短距离 位线接触根据存储单元在列方向上的位置而变化。 该方法包括在连续写入时从最近的存储单元顺序执行的写入操作，使得存储单元电流对于两个相邻位线触点之间的同一列上的所有或一些存储单元的电流变小 在列方向。

公开(公告)号：US07515480B2

公开(公告)日：2009-04-07

申请号：US11592043

申请日：2006-11-01

申请人： Masahiro Tomida ,  Naoki Ueda

发明人： Masahiro Tomida ,  Naoki Ueda

IPC分类号： G11C11/34

CPC分类号： G11C8/08 ,  G11C7/22 ,  G11C16/10

摘要： A nonvolatile semiconductor memory device and its writing method for reducing a writing rate variation without changing a voltage condition applied for each memory cell in writing operation is provided. The device comprises a memory cell array configuration where each drain of the memory cells on the same column is connected to a first bit line via a second bit line and a bit line contact, and the shortest distance from each drain of the memory cells to the bit line contact varies according to a location of the memory cell in the column direction. The method includes a writing operation carried out sequentially from the nearest memory cell to the bit line contact, upon writing continuously so that the memory cell current becomes small for all or some of the memory cells on the same column between the two adjacent bit line contacts in the column direction.

摘要翻译： 提供了一种非易失性半导体存储器件及其写入方法，用于在不改变在写入操作中对每个存储单元施加的电压条件的同时降低写入速率变化。 该器件包括存储单元阵列配置，其中同一列上的存储器单元的每个漏极经由第二位线和位线接触连接到第一位线，以及从存储器单元的每个漏极到第一位线的最短距离 位线接触根据存储单元在列方向上的位置而变化。 该方法包括在连续写入时从最近的存储单元顺序执行的写入操作，使得存储单元电流对于两个相邻位线触点之间的同一列上的所有或一些存储单元的电流变小 在列方向。

公开(公告)号：US09750085B2

公开(公告)日：2017-08-29

申请号：US13996886

申请日：2011-11-22

申请人： Keisuke Suzuki ,  Yuki Nakajima ,  Naoki Ueda

发明人： Keisuke Suzuki ,  Yuki Nakajima ,  Naoki Ueda

IPC分类号： H05B1/02 ,  B60H1/14 ,  B60H1/22 ,  H01M10/625 ,  H01M10/66

CPC分类号： H05B1/0227 ,  B60H1/143 ,  B60H1/2218 ,  H01M10/625 ,  H01M10/66

摘要： An apparatus for controlling a vehicle, which includes: a battery (3) capable of being charged from an external power source (EPS); a power generation unit (PGU) capable of charging the battery (3); an electric heater (12) configured to produce heat with electric power from an electric power source; a heater core (11) configured to heat air by using any one of waste heat from the power generation unit (PGU) and the electric heater (12); and a controller (19) configured to perform control for selectively using the waste heat from the power generation unit (PGU) and the electric heater (12) as a heat source of the heater core (11) when the vehicle is parked.

公开(公告)号：US09187035B2

公开(公告)日：2015-11-17

申请号：US13641619

申请日：2011-05-23

申请人： Yuki Nakajima ,  Keisuke Suzuki ,  Naoki Ueda

发明人： Yuki Nakajima ,  Keisuke Suzuki ,  Naoki Ueda

IPC分类号： B60Q1/54 ,  B60Q5/00 ,  B60W10/06 ,  B60W20/00

CPC分类号： B60Q5/008 ,  B60L3/00 ,  B60W10/06 ,  B60W20/00

摘要： A vehicle warning sound emitting apparatus includes a warning sound emitting component and a controller. The warning sound emitting component selectively emits a warning sound that is audible outside of the vehicle. The controller controls the warning sound emitting component to emit the warning sound during a prescribed period that an engine sound is being emitted from an engine of the vehicle such that the engine sound and the warning sound are audible at a location outside the vehicle during the prescribed period when the controller is controlling the warning sound emitting component to switch between emitting the warning sound and refraining from emitting the warning sound based on a vehicle traveling condition.

摘要翻译： 车辆警告声发射装置包括警告声发射部件和控制器。 警告声发射部件选择性地发出在车辆外部可听见的警告声音。 所述控制器控制所述警告声发射部件在规定期间发出警告声音，以使得发动机声音从所述车辆的发动机发出，使得所述发动机声音和所述警告声音在所述规定的车辆外部的位置处可听见 当控制器正在控制警告声发射部件以在发出警告声音之间切换并且基于车辆行驶状况不发出警告声音时。

公开(公告)号：US08947418B2

公开(公告)日：2015-02-03

申请号：US13989492

申请日：2011-10-05

申请人： Fumiki Nakano ,  Naoki Ueda ,  Yoshimitsu Yamauchi

发明人： Fumiki Nakano ,  Naoki Ueda ,  Yoshimitsu Yamauchi

IPC分类号： G09G5/00 ,  G09G3/36

CPC分类号： G09G3/3618 ,  G09G3/3648 ,  G09G2300/0876 ,  G09G2300/088 ,  G09G2310/08

摘要： A display device in which low power consumption is realized without lowering an aperture ratio is provided. A liquid crystal capacitive element Clc is sandwiched between a pixel electrode 20 and an opposite electrode 80. The pixel electrode 20, one end of a first switch circuit 22, one end of a second switch circuit 23 and a first terminal of a second transistor T2 form an internal node N1. The other terminals of the first switch circuit 22 and the second switch circuit 23 are connected to a source line SL. The second switch circuit 23 is a series circuit composed of a first transistor T1 and a diode D1. A control terminal of the first transistor T1, a second terminal of the second transistor T2 and one end of a boost capacitive element Cbst form an output node N2. The other end of the boost capacitive element Cbst and the control terminal of the second transistor T2 are connected to a boost line BST and a reference line REF, respectively. The diode D1 has a rectifying function from the source line SL to the internal node N1.

摘要翻译： 提供了一种在不降低开口率的情况下实现低功耗的显示装置。 液晶电容元件Clc被夹在像素电极20和相对电极80之间。像素电极20，第一开关电路22的一端，第二开关电路23的一端和第二晶体管T2的第一端 形成内部节点N1。 第一开关电路22和第二开关电路23的其他端子连接到源极线SL。 第二开关电路23是由第一晶体管T1和二极管D1组成的串联电路。 第一晶体管T1的控制端子，第二晶体管T2的第二端子和升压电容元件Cbst的一端形成输出节点N2。 升压电容元件Cbst的另一端和第二晶体管T2的控制端分别连接到升压线BST和基准线REF。 二极管D1具有从源极线SL到内部节点N1的整流功能。

公开(公告)号：US20110116316A1

公开(公告)日：2011-05-19

申请号：US12863234

申请日：2009-01-06

申请人： Naoki Ueda

发明人： Naoki Ueda

IPC分类号： G11C16/10 ,  H01L29/788

CPC分类号： H01L27/11521 ,  G11C16/0441

摘要： A nonvolatile random access memory that can be mounted on a substrate during a standard CMOS process. A memory cell comprises: a first MIS transistor including a first semiconductor layer of a first conductivity type in an electrically floating state, first drain and source regions of a second conductivity type formed on the first semiconductor layer, and a first gate electrode formed over the first semiconductor layer via a first gate insulating film; and a second MIS transistor including a second semiconductor layer of the first conductivity type isolated from the first semiconductor layer, second drain and source regions of the second conductivity type formed on the second semiconductor layer, a second gate electrode formed over the second semiconductor layer via a second gate insulating film. The first and second gate electrodes are electrically connected to each other so as to form a floating gate in an electrically floating state.

摘要翻译： 一种非易失性随机存取存储器，可在标准CMOS工艺过程中安装在衬底上。 存储单元包括：第一MIS晶体管，其包括处于浮置状态的第一导电类型的第一半导体层，形成在第一半导体层上的第二导电类型的第一漏极和源极区;以及第一栅电极， 第一半导体层经由第一栅极绝缘膜; 以及第二MIS晶体管，包括从第一半导体层隔离的第一导电类型的第二半导体层，形成在第二半导体层上的第二导电类型的第二漏极和源极区，形成在第二半导体层上的第二栅电极 第二栅极绝缘膜。 第一和第二栅电极彼此电连接以形成处于浮动状态的浮动栅极。

公开(公告)号：US20100278617A1

公开(公告)日：2010-11-04

申请号：US12662725

申请日：2010-04-30

申请人： Kazuhide Sano ,  Hideki Orii ,  Keiichi Nagasawa ,  Sei Takahashi ,  Naoki Ueda ,  Suguru Maruyama

发明人： Kazuhide Sano ,  Hideki Orii ,  Keiichi Nagasawa ,  Sei Takahashi ,  Naoki Ueda ,  Suguru Maruyama

IPC分类号： B42B9/00

CPC分类号： B26D1/08 ,  B26D7/025 ,  B26D7/088 ,  B26D7/20 ,  B26D2007/202 ,  B42C5/00 ,  B42C19/02 ,  Y10T83/4841 ,  Y10T83/9312

摘要： To provide a trimming apparatus that does not stain a fore edge end by an adhesive adhering to a blade receiving surface in trimming a bunch of sheets subjected to bookbinding using the adhesive, the trimming apparatus has a transport path 33 for feeding a bunch of sheets to a predetermined trimming position G, trimming blade 65x disposed in the trimming position, bunch position changing means 64 disposed in the transport path to change a position of the bunch of sheets in the trimming position, blade receiving member 67 disposed opposite to the trimming blade with the bunch of sheets in the transport path therebetween, and driving means Mc traveling between a cut position Cp for bringing the trimming blade into contact with the blade receiving member and a spaced waiting position Wp, where in the blade receiving member are set first and second, at least two, blade receiving areas with different blade receiving surfaces coming into contact with the trimming blade, while shift means MS for shifting positions between the first and second blade receiving areas is provided.

摘要翻译： 为了提供一种修剪装置，该修剪装置通过粘合到刀片接收表面上的粘合剂来染色前边缘端部，以修剪使用粘合剂进行装订的一束片材，修剪装置具有用于将一束片材进给的传送路径33 预定的修剪位置G，设置在修剪位置的修剪刀片65x，布置在传送路径中的束位置改变装置64，以改变修剪位置中的片材束的位置，与修剪刀片相对设置的刀片接收部件67， 在它们之间的传送路径中的一束片材以及在剪切刀片与刀片接收部件接触的切割位置Cp和间隔的等待位置Wp之间行进的驱动装置Mc，其中刀片接收部件中的第一和第二 具有不同刀片接收表面的至少两个刀片接收区域与修剪刀片接触，而移位装置MS 提供了用于在第一和第二刀片接收区域之间移位的位置。

公开(公告)号：US07630243B2

公开(公告)日：2009-12-08

申请号：US12094379

申请日：2006-11-01

申请人： Kaoru Yamamoto ,  Nobuhiko Ito ,  Naoki Ueda ,  Yoshimitsu Yamauchi

发明人： Kaoru Yamamoto ,  Nobuhiko Ito ,  Naoki Ueda ,  Yoshimitsu Yamauchi

IPC分类号： G11C16/04

CPC分类号： G11C16/0491 ,  G11C16/24 ,  G11C16/26

摘要： A virtual ground type semiconductor memory device comprises: a memory cell array in which nonvolatile memory cells each including a first electrode, a pair of second electrodes, and a charge retention part are arranged in row and column directions like a matrix; a read circuit for selecting a pair of the first and second bit lines connected to a selected memory cell to be read, applying first and second read voltages to the selected first and second bit lines, respectively, and detecting a magnitude of a memory cell current flowing in the selected memory cell, at the time of reading; a voltage applying means for applying the second read voltage to a second adjacent bit line adjacent to the selected second bit line on the opposite side of the first bit line; and a short-circuit means for short-circuiting the selected second bit line and the second adjacent bit line.

摘要翻译： 虚拟接地型半导体存储器件包括：存储单元阵列，其中包括第一电极，一对第二电极和电荷保持部分的非易失性存储单元排列成像矩阵的行和列方向; 读取电路，用于选择连接到要读取的所选择的存储器单元的一对第一和第二位线，将第一和第二读取电压分别施加到所选择的第一和第二位线，并且检测存储单元电流的大小 在读取时流入所选存储单元; 电压施加装置，用于将第二读取电压施加到与第一位线的相对侧上的所选择的第二位线相邻的第二相邻位线; 以及用于短路所选择的第二位线和第二相邻位线的短路装置。

公开(公告)号：US20060083067A1

公开(公告)日：2006-04-20

申请号：US11251059

申请日：2005-10-14

申请人： Naoki Ueda

发明人： Naoki Ueda

IPC分类号： G11C16/04

CPC分类号： G11C16/3459 ,  G11C16/04 ,  G11C16/12 ,  G11C16/3436 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50004

摘要： A method for determining programming voltage of a nonvolatile memory in which any variation in the threshold voltage at the memory cell after programming by hot carrier injection can be suppressed includes the steps of: setting the drain voltage to an initial setting level; applying the drain voltage and a gate voltage at a predetermined programming time; shifting the drain voltage to another setting level; reprogramming the memory cell with the another setting level of the drain voltage; measuring the threshold voltage of the memory cell; and determining a differential represented by a ratio of a change in the threshold voltage to a change in the drain voltage at the threshold voltage after the reprogramming, whereby when the determined differential and the measured threshold voltage remain within their respective permissible ranges, the setting determined by the shifting step is defined as an optimum level of the drain voltage.

摘要翻译： 一种用于确定非易失性存储器的编程电压的方法，其中可以抑制通过热载流子注入编程之后的存储单元处的阈值电压的任何变化，包括以下步骤：将漏极电压设置为初始设置电平; 在预定的编程时间施加漏极电压和栅极电压; 将漏极电压移至另一设定电平; 以另一设定电平重新编程存储单元; 测量存储器单元的阈值电压; 并且确定由所述阈值电压的变化与所述重新编程之后的所述阈值电压下的所述漏极电压的变化的比率所表示的差值，由此当所确定的差值和所测量的阈值电压保持在其各自的允许范围内时，所述设定被确定 通过移位步骤被定义为漏极电压的最佳电平。

公开(公告)号：US06969885B2

公开(公告)日：2005-11-29

申请号：US10732475

申请日：2003-12-11

申请人： Tadahiro Omi ,  Naoki Ueda

发明人： Tadahiro Omi ,  Naoki Ueda

IPC分类号： H01L21/8234 ,  H01L21/28 ,  H01L21/318 ,  H01L21/8247 ,  H01L27/088 ,  H01L27/10 ,  H01L27/115 ,  H01L29/423 ,  H01L29/51 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11526 ,  H01L21/28273 ,  H01L27/11546 ,  H01L29/42324 ,  H01L29/511

摘要： A non-volatile semiconductor memory device comprising at least: a first electrode containing silicon atoms; and a second electrode formed on the first electrode through an insulating film, wherein the insulating film is formed of at least two layers of: a lower silicon nitride film on the first electrode side obtained by nitriding the first electrode; and an upper silicon nitride film formed on the lower silicon nitride film according to a chemical vapor deposition method, and at least a part of the lower silicon nitride film contains a rare gas element at an area density of 1010 cm−2 or more.

摘要翻译： 一种非挥发性半导体存储器件，至少包括：含有硅原子的第一电极; 以及通过绝缘膜形成在所述第一电极上的第二电极，其中所述绝缘膜由至少两层形成：通过氮化所述第一电极而获得的所述第一电极侧的下氮化硅膜; 以及根据化学气相沉积法形成在下部氮化硅膜上的上部氮化硅膜，并且至少一部分下部氮化硅膜含有10 <10/10的面积密度的稀有气体元素 > cm 2以上。