公开(公告)号：US08455977B2

公开(公告)日：2013-06-04

申请号：US13466986

申请日：2012-05-08

申请人： Wei Xia ,  Xiangdong Chen ,  Akira Ito

发明人： Wei Xia ,  Xiangdong Chen ,  Akira Ito

IPC分类号： H01L29/00

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one exemplary embodiment, a method for forming a one-time programmable metal fuse structure includes forming a metal fuse structure over a substrate, the metal fuse structure including a gate metal segment situated between a dielectric segment and a polysilicon segment, a gate metal fuse being formed in a portion of the gate metal segment. The method further includes doping the polysilicon segment so as to form first and second doped polysilicon portions separated by an undoped polysilicon portion where, in one embodiment, the gate metal fuse is substantially co-extensive with the undoped polysilicon portion. The method can further include forming a first silicide segment on the first doped polysilicon portion and a second silicide segment on the second doped polysilicon portion, where the first and second silicide segments form respective terminals of the one-time programmable metal fuse structure.

摘要翻译： 根据一个示例性实施例，一种用于形成一次性可编程金属熔丝结构的方法包括在衬底上形成金属熔丝结构，所述金属熔丝结构包括位于介电段和多晶硅段之间的栅极金属段，栅极金属 熔丝形成在栅极金属段的一部分中。 该方法还包括掺杂多晶硅段以便形成由未掺杂多晶硅部分分开的第一和第二掺杂多晶硅部分，其中在一个实施例中，栅极金属熔丝与未掺杂的多晶硅部分基本上共同延伸。 该方法还可以包括在第一掺杂多晶硅部分上形成第一硅化物部分和在第二掺杂多晶硅部分上形成第二硅化物部分，其中第一和第二硅化物部分形成一次性可编程金属熔丝结构的相应端子。

公开(公告)号：US20130105942A1

公开(公告)日：2013-05-02

申请号：US13287331

申请日：2011-11-02

申请人： Xiangdong Chen ,  Henry Chen ,  Agnes Woo ,  Wei Xia

发明人： Xiangdong Chen ,  Henry Chen ,  Agnes Woo ,  Wei Xia

IPC分类号： H01L29/92 ,  H01L21/02

CPC分类号： H01L29/785 ,  H01L28/20 ,  H01L29/66795 ,  H01L29/7855 ,  H01L29/7856 ,  H01L29/94

摘要： Disclosed are various embodiments of FinFET semiconductor devices. A pair of matched capacitors can be formed that share a common source, drain and/or channel. Accordingly, the capacitance characteristics of each capacitor can be manufactured such that they are similar to one another. A resistor manufactured by employing FinFET techniques is also described. The resistor can be manufactured with an effective length that is greater than a distance traversed along a substrate by the resistor.

摘要翻译： 公开了FinFET半导体器件的各种实施例。 可以形成一对共用的源极，漏极和/或沟道的匹配电容器。 因此，可以制造每个电容器的电容特性使得它们彼此相似。 还描述了采用FinFET技术制造的电阻器。 电阻器可以制造成有效长度大于通过电阻器沿衬底穿过的距离。

公开(公告)号：US20130082325A1

公开(公告)日：2013-04-04

申请号：US13252880

申请日：2011-10-04

申请人： Akira Ito ,  Xiangdong Chen

发明人： Akira Ito ,  Xiangdong Chen

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7816 ,  H01L21/76224 ,  H01L23/5252 ,  H01L27/088 ,  H01L27/11206 ,  H01L27/11226 ,  H01L27/1124 ,  H01L27/11246 ,  H01L27/11266 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66681 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one embodiment, a one-time programmable (OTP) device having a lateral diffused metal-oxide-semiconductor (LDMOS) structure comprises a pass gate including a pass gate electrode and a pass gate dielectric, and a programming gate including a programming gate electrode and a programming gate dielectric. The programming gate is spaced from the pass gate by a drain extension region of the LDMOS structure. The LDMOS structure provides protection for the pass gate when a programming voltage for rupturing the programming gate dielectric is applied to the programming gate electrode. A method for producing such an OTP device comprises forming a drain extension region, fabricating a pass gate over a first portion of the drain extension region, and fabricating a programming gate over a second portion of the drain extension region.

摘要翻译： 根据一个实施例，具有横向扩散的金属氧化物半导体（LDMOS）结构的一次性可编程（OTP）器件包括包括通过栅极电极和通过栅极电介质的通过栅极，以及包括编程门 电极和编程栅极电介质。 编程门通过LDMOS结构的漏极扩展区与通过栅极间隔开。 当用于将编程栅极电介质破裂的编程电压施加到编程栅电极时，LDMOS结构为通路提供保护。 一种用于制造这种OTP器件的方法包括形成漏极延伸区域，在漏极延伸区域的第一部分上制造栅极通孔，以及在漏极延伸区域的第二部分上制造编程栅极。

公开(公告)号：US20130001687A1

公开(公告)日：2013-01-03

申请号：US13613864

申请日：2012-09-13

申请人： Xiangdong Chen ,  Wei Xia ,  Henry Kuo-Shun Chen

发明人： Xiangdong Chen ,  Wei Xia ,  Henry Kuo-Shun Chen

IPC分类号： H01L29/78

CPC分类号： H01L29/0878 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/66537 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/7835

摘要： According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a self-aligned lightly doped region in a first well underlying a first sidewall of a gate. The method further includes forming a self-aligned extension region under a second sidewall of the gate, where the self-aligned extension region extends into the first well from a second well. The method further includes forming a drain region spaced apart from the second sidewall of the gate. The method further includes forming a source region in the self-aligned lightly doped region and the first well. The self-aligned lightly doped region and the self-aligned extension region define a channel length of the MOS transistor, such as an LDMOS transistor.

摘要翻译： 根据示例性实施例，用于制造诸如LDMOS晶体管的MOS晶体管的方法包括在栅极的第一侧壁下面的第一阱中形成自对准的轻掺杂区域。 该方法还包括在栅极的第二侧壁下方形成自对准延伸区域，其中自对准延伸区域从第二阱延伸到第一阱中。 该方法还包括形成与栅极的第二侧壁间隔开的漏极区域。 该方法还包括在自对准轻掺杂区域和第一阱中形成源极区域。 自对准轻掺杂区域和自对准延伸区域限定诸如LDMOS晶体管的MOS晶体管的沟道长度。

公开(公告)号：US08237197B2

公开(公告)日：2012-08-07

申请号：US12831310

申请日：2010-07-07

申请人： Xiangdong Chen ,  Jie Deng ,  Weipeng Li ,  Deleep R. Nair ,  Jae-Eun Park ,  Daniel Tekleab ,  Xiaobin Yuan ,  Nam Sung Kim

发明人： Xiangdong Chen ,  Jie Deng ,  Weipeng Li ,  Deleep R. Nair ,  Jae-Eun Park ,  Daniel Tekleab ,  Xiaobin Yuan ,  Nam Sung Kim

IPC分类号： H01L29/66

CPC分类号： H01L21/823412 ,  H01L21/28202 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7835

摘要： A field effect transistor includes a partial SiGe channel, i.e., a channel including a SiGe channel portion, located underneath a gate electrode and a Si channel portion located underneath an edge of the gate electrode near the drain region. The SiGe channel portion can be located directly underneath a gate dielectric, or can be located underneath a Si channel layer located directly underneath a gate dielectric. The Si channel portion is located at the same depth as the SiGe channel portion, and contacts the drain region of the transistor. By providing a Si channel portion near the drain region, the GIDL current of the transistor is maintained at a level on par with the GIDL current of a transistor having a silicon channel only during an off state.

摘要翻译： 场效应晶体管包括部分SiGe沟道，即包括位于栅极下方的SiGe沟道部分的沟道部分，以及位于漏极区域附近的位于栅电极的边缘下方的Si沟道部分。 SiGe沟道部分可以位于栅极电介质的正下方，或者可以位于位于栅极电介质正下方的Si沟道层下方。 Si沟道部分位于与SiGe沟道部分相同的深度处，并与晶体管的漏极区域接触。 通过在漏极区附近提供Si沟道部分，晶体管的GIDL电流仅在断开状态下保持在与具有硅沟道的晶体管的GIDL电流相同的水平上。

公开(公告)号：US20120039106A1

公开(公告)日：2012-02-16

申请号：US13283418

申请日：2011-10-27

申请人： Frank Hui ,  Xiangdong Chen ,  Wei Xia

发明人： Frank Hui ,  Xiangdong Chen ,  Wei Xia

IPC分类号： G11C17/08

CPC分类号： G11C17/16 ,  G11C17/18 ,  H01L27/115

摘要： According to one exemplary embodiment, a one-time programmable memory cell includes an access transistor coupled to a shiftable threshold voltage transistor between a bitline and a ground, where the access transistor has a gate coupled to a wordline. The shiftable threshold voltage transistor has a drain and a gate shorted together. A programming operation causes a permanent shift in a threshold voltage of the shiftable threshold voltage transistor to occur in response to a programming voltage on the bitline and the wordline. In one embodiment, the access transistor is an NFET while the shiftable threshold voltage transistor is a PFET. In another embodiment, the access transistor is an NFET and the shiftable threshold voltage transistor is also an NFET. The programming voltage can cause an absolute value of the threshold voltage to permanently increase by at least 50.0 millivolts.

摘要翻译： 根据一个示例性实施例，一次性可编程存储器单元包括耦合到位线和地之间的可移位阈值电压晶体管的存取晶体管，其中存取晶体管具有耦合到字线的栅极。 可移位阈值电压晶体管具有漏极和栅极短路在一起。 编程操作导致响应于位线和字线上的编程电压而发生可移位阈值电压晶体管的阈值电压的永久偏移。 在一个实施例中，存取晶体管是NFET，而可移位阈值电压晶体管是PFET。 在另一个实施例中，存取晶体管是NFET，而可移位阈值电压晶体管也是NFET。 编程电压可导致阈值电压的绝对值永久增加至少50.0毫伏。

公开(公告)号：US08089118B2

公开(公告)日：2012-01-03

申请号：US12456065

申请日：2009-06-10

申请人： Xiangdong Chen ,  Henry Kuo-Shun Chen ,  Kent Charles Oertle ,  Jennifer Chiao

发明人： Xiangdong Chen ,  Henry Kuo-Shun Chen ,  Kent Charles Oertle ,  Jennifer Chiao

IPC分类号： H01L29/788 ,  H01L29/792 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L29/66575 ,  H01L21/26586 ,  H01L29/1045 ,  H01L29/66537 ,  H01L29/78

摘要： According to one embodiment, a method for selective gate halo implantation includes forming at least one gate having a first orientation and at least one gate having a second orientation over a substrate. The method further includes performing a halo implant over the substrate. The first orientation allows a halo implanted area to be formed under the at least one gate having the first orientation and the second orientation prevents a halo implanted area from forming under the at least one gate having the second orientation. The halo implant is performed without forming a mask over the at least one gate having the first orientation or the at least one gate having the second orientation. The at least one gate having the first orientation can be used in a low voltage region of a substrate, while the at least one gate having the second orientation can be used in a high voltage region.

摘要翻译： 根据一个实施例，用于选择性栅极晕晕注入的方法包括在衬底上形成具有第一取向的至少一个栅极和具有第二取向的至少一个栅极。 该方法还包括在衬底上执行晕轮植入。 第一取向允许在具有第一取向的至少一个栅极下方形成光晕注入区域，并且第二取向防止在具有第二取向的至少一个栅极下形成光晕注入区域。 在没有在具有第一取向的至少一个栅极或具有第二取向的至少一个栅极上形成掩模的情况下执行光晕注入。 具有第一取向的至少一个栅极可用于衬底的低电压区域，而具有第二取向的至少一个栅极可用于高电压区域。

公开(公告)号：US20110049620A1

公开(公告)日：2011-03-03

申请号：US12583977

申请日：2009-08-28

申请人： Xiangdong Chen ,  Bruce Chih-Chieh Shen ,  Henry Kuo-Shun Chen

发明人： Xiangdong Chen ,  Bruce Chih-Chieh Shen ,  Henry Kuo-Shun Chen

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7816 ,  H01L29/0653 ,  H01L29/0856 ,  H01L29/086 ,  H01L29/165 ,  H01L29/267 ,  H01L29/6656 ,  H01L29/66689 ,  H01L29/7848

摘要： According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a gate stack over a well. The method further includes forming a recess in the well adjacent to a first sidewall of the gate stack. The method further includes forming a source region in the recess such that a heterojunction is formed between the source region and the well. The method further includes forming a drain region spaced apart from a second sidewall of the gate stack. In one embodiment, the source region can comprise silicon germanium and the well can comprise silicon. In another embodiment, the source region can comprise silicon carbide and the well can comprise silicon.

摘要翻译： 根据示例性实施例，用于制造诸如LDMOS晶体管的MOS晶体管的方法包括在阱上形成栅极堆叠。 所述方法还包括在所述阱中形成与所述栅极堆叠的第一侧壁相邻的凹部。 该方法还包括在凹部中形成源极区域，使得在源区域和阱之间形成异质结。 该方法还包括形成与栅极堆叠的第二侧壁间隔开的漏极区域。 在一个实施例中，源极区域可以包括硅锗，并且阱可以包括硅。 在另一个实施例中，源极区域可以包括碳化硅，阱可以包括硅。

公开(公告)号：US07867839B2

公开(公告)日：2011-01-11

申请号：US12176634

申请日：2008-07-21

申请人： Xiangdong Chen ,  Jong Ho Lee ,  Weipeng Li ,  Dae-Gyu Park ,  Kenneth J. Stein ,  Voon-Yew Thean

发明人： Xiangdong Chen ,  Jong Ho Lee ,  Weipeng Li ,  Dae-Gyu Park ,  Kenneth J. Stein ,  Voon-Yew Thean

IPC分类号： H01L21/8238

CPC分类号： H01L21/823857 ,  H01L21/2652 ,  H01L21/823807 ,  H01L29/1054

摘要： Disclosed are embodiments of a p-type, silicon germanium (SiGe), high-k dielectric-metal gate, metal oxide semiconductor field effect transistor (PFET) having an optimal threshold voltage (Vt), a complementary metal oxide semiconductor (CMOS) device that includes the PFET and methods of forming both the PFET alone and the CMOS device. The embodiments incorporate negatively charged ions (e.g., fluorine (F), chlorine (Cl), bromine (Br), iodine (I), etc.) into the high-k gate dielectric material of the PFET only so as to selectively adjust the negative Vt of the PFET (i.e., so as to reduce the negative Vt of the PFET).

摘要翻译： 公开了具有最佳阈值电压（Vt）的p型硅锗（SiGe），高k电介质金属栅极，金属氧化物半导体场效应晶体管（PFET），互补金属氧化物半导体（CMOS）器件 其包括PFET和形成PFET单独和CMOS器件的方法。 实施例将带负电荷的离子（例如，氟（F），氯（Cl），溴（Br），碘（I）等）并入PFET的高k栅介质材料中，以便选择性地调节 PFET的负Vt（即，以减小PFET的负Vt）。

公开(公告)号：US20090291540A1

公开(公告)日：2009-11-26

申请号：US12125855

申请日：2008-05-22

申请人： Da Zhang ,  Srikanth B. Samavedam ,  Voon-Yew Thean ,  Xiangdong Chen

发明人： Da Zhang ,  Srikanth B. Samavedam ,  Voon-Yew Thean ,  Xiangdong Chen

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/26506 ,  H01L21/823814 ,  H01L29/1054 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/7843 ,  H01L29/7848

摘要： A semiconductor process and apparatus includes forming NMOS and PMOS transistors (24, 34) with enhanced hole mobility in the channel region of a transistor by selectively relaxing part of a biaxial-tensile strained semiconductor layer (90) in a PMOS device area (97) to form a relaxed semiconductor layer (91), and then epitaxially growing a bi-axially stressed silicon germanium channel region layer (22) prior to forming the NMOS and PMOS gate structures (26, 36) overlying the channel regions, and then depositing a contact etch stop layer (53-56) over the NMOS and PMOS gate structures. Embedded silicon germanium source/drain regions (84) may also be formed adjacent to the PMOS gate structure (70) to provide an additional uni-axial stress to the bi-axially stressed channel region.

摘要翻译： 半导体工艺和装置包括通过选择性地缓解PMOS器件区域（97）中的双轴拉伸应变半导体层（90）的一部分，在晶体管的沟道区域中形成具有增强的空穴迁移率的NMOS和PMOS晶体管（24,34） 以形成松弛半导体层（91），然后在形成覆盖沟道区域的NMOS和PMOS栅极结构（26,36）之前外延生长双轴向应力硅锗沟道区域层（22），然后沉积 接触蚀刻停止层（53-56）在NMOS和PMOS栅极结构之上。 也可以在PMOS栅极结构（70）附近形成嵌入硅锗源极/漏极区（84），以向双轴向应力沟道区提供额外的单轴应力。