公开(公告)号：US20170294921A1

公开(公告)日：2017-10-12

申请号：US15485020

申请日：2017-04-11

Applicant: Microchip Technology Incorporated

Inventor： Bryan Kris ,  Neil Deutscher ,  Tom Spohrer

IPC: H03M1/34 ,  H03K5/14 ,  H03K5/131 ,  H03M1/10

CPC classification number: H03M1/34 ,  H03K5/131 ,  H03K5/14 ,  H03K2005/00058 ,  H03M1/007 ,  H03M1/1009 ,  H03M1/1028 ,  H03M1/1057 ,  H03M1/1071 ,  H03M1/18 ,  H03M1/38 ,  H03M1/502

Abstract: Embodiments of the present disclosure include a differential digital delay line analog-to-digital converter (ADC), comprising differential digital delay lines including series coupled delay cells, wherein a delay time of a first delay line is controlled by a first input of the ADC and a delay time of a second delay line is controlled by a second input of the ADC. The ADC includes a pair of bypass multiplexers coupled at a predefined node location in the series coupled delay cells, latches each coupled with the series coupled delay cells, a converter circuit coupled with the plurality of latches configured to convert data from the latches into an output value of the ADC, and logic circuits configured to select data from the series coupled delay cells to the latches depending on a selected resolution of the differential digital delay line analog-to-digital converter.

公开(公告)号：US20150356039A1

公开(公告)日：2015-12-10

申请号：US14729402

申请日：2015-06-03

Applicant: MICROCHIP TECHNOLOGY INCORPORATED

Inventor： Bryan Kris

IPC: G06F13/38 ,  G06F13/28

CPC classification number: G06F13/385 ,  G06F1/22 ,  G06F13/287 ,  G06F15/76

Abstract: An embedded device has a plurality of processor cores, each with a plurality of peripheral devices, wherein each peripheral device may have an output, a housing with a plurality of assignable external pins, and a plurality of peripheral pin selection modules for each processing core, wherein each peripheral pin selection module is configured to be programmable to assign an assignable external pin to one of the plurality of peripheral devices of one of the processor cores.

Abstract translation: 嵌入式设备具有多个处理器核心，每个处理器核心具有多个外围设备，其中每个外围设备可以具有输出，具有多个可分配的外部引脚的外壳以及用于每个处理核心的多个外围引脚选择模块， 其中每个外围引脚选择模块被配置为可编程以将可分配的外部引脚分配给所述处理器核心之一的所述多个外围设备之一。

公开(公告)号：US20150249446A1

公开(公告)日：2015-09-03

申请号：US14714315

申请日：2015-05-17

Applicant: Microchip Technology Incorporated

Inventor： Bryan Kris

IPC: H03K7/08 ,  H03K3/017

CPC classification number: H03K7/08 ,  H03K3/017 ,  H03M1/68 ,  H03M1/822

Abstract: Using a combination of frequency dithering of a PWM counter and a variable time delay circuit yields improved PWM frequency resolution with realizable circuit components and clock operating frequencies. A controllable time delay circuit lengthens a PWM signal during the first PWM cycle. During the second PWM cycle, the PWM period is increased beyond the desired amount, but the delay is reduced during this second PWM cycle to achieve the correct (desired) PWM signal period. The dithering of the PWM signal period enables the time delay circuit to be “reset” so that an infinite delay circuit is not required. The time delay circuit provides short term (one cycle) frequency adjustment so that the resulting PWM cycle is not dithered and has a period at the desired frequency resolution.

Abstract translation: 使用PWM计数器的频率抖动和可变时间延迟电路的组合可以实现可实现的电路组件和时钟工作频率的改进的PWM频率分辨率。 可控延时电路在第一个PWM周期期间延长PWM信号。 在第二个PWM周期期间，PWM周期增加超过所需的量，但是在该第二个PWM周期期间延迟减小以实现正确的（期望的）PWM信号周期。 PWM信号周期的抖动使得时间延迟电路“复位”，从而不需要无限延迟电路。 时间延迟电路提供短期（一个周期）频率调整，使得所得到的PWM周期不抖动，并具有期望频率分辨率的周期。

公开(公告)号：US09048863B2

公开(公告)日：2015-06-02

申请号：US14202420

申请日：2014-03-10

Applicant: Microchip Technology Incorporated

Inventor： Bryan Kris ,  Andreas Reiter ,  Tibor Futo ,  Alex Dumais

IPC: H03M1/66 ,  H02M3/157 ,  H02M3/335

CPC classification number: H03M1/66 ,  H02M3/157 ,  H02M3/33515 ,  H03M3/502 ,  H03M7/3028 ,  H03M7/3042

Abstract: A slope compensation module provides slope compensation of a switched-mode power supply using current mode control. This slope compensation function may be provided by a digital slope compensation generator and a pulse density modulated digital-to-analog converter (PDM DAC) having a selectable response mode low pass filter.

Abstract translation: 坡度补偿模块使用电流模式控制提供开关模式电源的斜率补偿。 该斜率补偿功能可以由具有可选择的响应模式低通滤波器的数字斜率补偿发生器和脉冲密度调制数模转换器（PDM DAC）提供。