中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

90 records (took 0.017 seconds)

    Programming method, reading method and operating system for memory
    62.
    发明授权
    Programming method, reading method and operating system for memory 有权
    存储器的编程方法，读取方法和操作系统

    公开(公告)号：US09286158B2

    公开(公告)日：2016-03-15

    申请号：US14173873

    申请日：2014-02-06

    Applicant: Macronix International Co., Ltd.

    Inventor： Chien-Hsin Liu ,  Su-Chueh Lo ,  Kuen-Long Chang ,  Ken-Hui Chen ,  Chun-Hsiung Hung

    IPC: G06F11/00 ,  H03M13/00 ,  G06F11/10 ,  H03M13/19 ,  H03M13/15

    CPC classification number: G06F11/1072 ,  G06F11/1012 ,  H03M13/1575 ,  H03M13/19

    Abstract: A programming method, a reading method and an operating system for a memory are provided. The programming method includes the following steps. A data is provided. A parity generation is performed to obtain an error-correcting code (ECC). The memory is programmed to record the data and the error-correcting code. The data is transformed before performing the parity generation, such that a hamming distance between two codes corresponding to two adjacent threshold voltage states in the data to be performed the parity generation is 1.

    Abstract translation: 提供了一种用于存储器的编程方法，读取方法和操作系统。 编程方法包括以下步骤。 提供数据。 执行奇偶校验生成以获得纠错码（ECC）。 存储器被编程为记录数据和纠错码。 在执行奇偶校验生成之前变换数据，使得对应于待执行奇偶产生的数据中的两个相邻阈值电压状态的两个代码之间的汉明距离为1。

    Self-calibration of output buffer driving strength
    64.
    发明授权
    Self-calibration of output buffer driving strength 有权

    公开(公告)号：US08847635B2

    公开(公告)日：2014-09-30

    申请号：US14158033

    申请日：2014-01-17

    Applicant: Macronix International Co., Ltd.

    Inventor： Yu-Meng Chaung ,  Chun-Hsiung Hung ,  Kuen-Long Chang ,  Ken-Hui Chen

    IPC: H03K3/00

    CPC classification number: H03K17/145 ,  H03K19/00384 ,  H03K2005/00026

    Abstract: An integrated circuit includes an output buffer and a control circuit. The output buffer has a signal input, a signal output, and a set of control inputs. The output buffer has an output buffer delay, and a driving strength adjustable in response to control signals applied to the set of control inputs. The control circuit is connected to the set of control inputs of the output buffer. The control circuit uses first and second timing signals to generate the control signals, and includes a reference delay circuit that generates the first timing signal with a reference delay, and a delay emulation circuit that generates the second timing signal with an emulation delay that correlates with the output buffer delay.

    METHOD AND APPARATUS FOR THE ERASE SUSPEND OPERATION
    66.
    发明申请
    METHOD AND APPARATUS FOR THE ERASE SUSPEND OPERATION 有权
    擦除操作的方法和装置

    公开(公告)号：US20130294173A1

    公开(公告)日：2013-11-07

    申请号：US13936620

    申请日：2013-07-08

    Applicant: Macronix International Co., Ltd.

    Inventor： Chuan-Ying Yu ,  Ken-Hui Chen ,  Chun-Hsiung Hung ,  Kuen-Long Chang

    IPC: G11C16/16

    CPC classification number: G11C16/16 ,  G11C16/345 ,  G11C16/3454

    Abstract: Various aspects of a nonvolatile memory have an improved erase suspend procedure. A bias arrangement is applied to word lines of an erase sector undergoing an erase procedure interrupted by an erase suspend procedure. As a result, another operation performed during erase suspend, such as a read operation or program operation, has more accurate results due to decreased leakage current from any over-erased nonvolatile memory cells of the erase sector.

    Abstract translation: 非易失性存储器的各个方面具有改进的擦除暂停过程。 偏移布置被施加到经历由擦除暂停过程中断的擦除过程的擦除扇区的字线。 结果，由于擦除扇区的任何被擦除的非易失性存储单元的漏电流减少，因此在诸如读操作或程序操作的擦除暂停期间执行的另一操作具有更精确的结果。

    Method and system for a serial peripheral interface
    69.
    再颁专利
    Method and system for a serial peripheral interface 有权

    公开(公告)号：USRE49125E1

    公开(公告)日：2022-07-05

    申请号：US16734882

    申请日：2020-01-06

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Chia-He Liu

    IPC: G11C7/10 ,  G11C7/22

    Abstract: An integrated circuit includes a serial peripheral interface memory device. In an embodiment, the memory device includes a clock signal, a plurality of pins, and a configuration register. In an embodiment, the configuration register includes a wait cycle count. The method includes transmitting a read address to the memory device using a first input/output pin and a second input/output pin concurrently. In an embodiment, the read address includes at least a first address bit and a second address bit, the first address bit being transmitted using the first input/output pin, and the second address bit being transmitted using the second input/output pin. The method includes accessing the memory device for data associated with the address and waiting a predetermined number clock cycles associated with the wait cycle count. The method includes transferring the data from the memory device using the first input/output pin and the second input/output pin concurrently.

Patent Agency Ranking