公开(公告)号：US08009470B2

公开(公告)日：2011-08-30

申请号：US12563296

申请日：2009-09-21

申请人： Makoto Iwai ,  Hiroshi Nakamura

发明人： Makoto Iwai ,  Hiroshi Nakamura

IPC分类号： G11C16/04

CPC分类号： G11C16/3459 ,  G11C11/56 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  G11C16/26 ,  G11C16/3436 ,  G11C16/3454

摘要： A memory includes first and second select gate transistors, memory cells, a source line, a bit line, a selected word line which is connected to a selected memory cell as a target of a verify reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line, and a control circuit which classifies a threshold voltage of the selected memory cell to one of three groups by verifying which area among three area which are isolated by two values does a cell current of the selected memory cell belong, when the selected read potential is a first value.

摘要翻译： 存储器包括第一和第二选择栅极晶体管，存储器单元，源极线，位线，连接到作为验证读取的目标的所选存储单元的选定字线，连接的未选择字线 到除所选存储单元之外的未选择的存储单元，用于产生提供给所选择的字线的所选择的读取电位并产生大于所选择的读取电位的未被选择的读取电位的电位产生电路， 以及控制电路，其通过验证被选择的存储器单元的单元电流属于两个值隔离的三个区域中的哪个区域属于三个组中的一个，将选择的存储单元的阈值电压分类为三个组中的一个 当所选择的读取电位为第一值时。

公开(公告)号：US07995389B2

公开(公告)日：2011-08-09

申请号：US12563274

申请日：2009-09-21

申请人： Makoto Iwai

发明人： Makoto Iwai

IPC分类号： G11C16/04

CPC分类号： G11C11/5642 ,  G11C16/0483 ,  G11C2211/5621

摘要： A memory includes first and second select gate transistors, memory cells which are connected in series between the first and second select gate transistors, a selected word line which is connected to a selected memory cell as a target of a reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line, and a control circuit which changes a set up term of the selected word line and the non-selected word line based on a value of the selected read potential, wherein the value of the selected read potential is selected from two or more potentials.

摘要翻译： 存储器包括第一和第二选择栅极晶体管，串联连接在第一和第二选择栅极晶体管之间的存储单元，连接到所选存储单元作为读取目标的选定字线，未被选择的字 线路，其连接到除所选择的存储器单元之外的未选择的存储器单元;电位产生电路，用于产生提供给所选择的字线的所选择的读取电位，以及产生大于所选择的读取电位的未选择的读取电位 ，其被提供给未选择的字线，以及控制电路，其基于所选择的读取电位的值来改变所选字线和未选择的字线的设置项，其中所选择的 从两个或更多个电位中选择读取电位。

公开(公告)号：US07859901B2

公开(公告)日：2010-12-28

申请号：US12329007

申请日：2008-12-05

申请人： Makoto Iwai ,  Kazuhisa Kanazawa ,  Hiroshi Nakamura ,  Masaki Fujiu

发明人： Makoto Iwai ,  Kazuhisa Kanazawa ,  Hiroshi Nakamura ,  Masaki Fujiu

IPC分类号： G11C11/34

CPC分类号： G11C16/16 ,  G11C16/0483 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529

摘要： A semiconductor memory device includes a memory cell array including a plurality of blocks each including a memory cell unit, and a selection transistor which selects the memory cell unit, and a row decoder including a first block selector and a second block selector each of which includes a plurality of transfer transistors which are formed to correspond to the plurality of blocks and arranged adjacent to each other in a word-line direction wherein the diffusion layers are formed to oppose each other in the first block selector and the second block selector, and a width between the diffusion layers of the first block selector and the second block selector adjacent to each other in the word-line direction is made larger than a width between the diffusion layers in each of the first block selector and the second block selector adjacent to each other in the word-line direction.

摘要翻译： 半导体存储器件包括存储单元阵列，其包括多个块，每个块包括存储单元单元和选择存储单元单元的选择晶体管;以及行解码器，包括第一块选择器和第二块选择器，每个块选择器包括 多个传输晶体管，其被形成为对应于多个块并且在字线方向上彼此相邻布置，其中扩散层在第一块选择器和第二块选择器中形成为彼此相对，并且 使第一块选择器的扩散层与字线方向上彼此相邻的第二块选择器之间的宽度大于与第一块选择器和第二块选择器相邻的第一块选择器和第二块选择器中的每一个中的扩散层之间的宽度 其他在字线方向。

公开(公告)号：US07842133B2

公开(公告)日：2010-11-30

申请号：US12190230

申请日：2008-08-12

申请人： Makoto Iwai ,  Takanao Shimodaira ,  Shuhei Higashihara ,  Takatomo Sasaki ,  Yusuke Mori ,  Fumio Kawamura ,  Shiro Yamasaki ,  Koji Hirata

发明人： Makoto Iwai ,  Takanao Shimodaira ,  Shuhei Higashihara ,  Takatomo Sasaki ,  Yusuke Mori ,  Fumio Kawamura ,  Shiro Yamasaki ,  Koji Hirata

IPC分类号： C30B27/02 ,  C30B28/10

CPC分类号： C30B29/406 ,  C30B9/10 ,  C30B17/00 ,  C30B19/02 ,  C30B19/063

摘要： In a method of growing a single crystal by melting a raw material within a vessel under a nitrogenous and non-oxidizing atmosphere, the vessel is oscillated and the melted raw material is contacted with an agitation medium made of a solid unreactive with the melted raw material.

摘要翻译： 在通过在氮气和非氧化气氛下在容器内熔化原料而生长单晶的方法中，容器振荡，使熔融的原料与由熔融的原料不反应的固体的搅拌介质接触 。

公开(公告)号：US20100177563A1

公开(公告)日：2010-07-15

申请号：US12730330

申请日：2010-03-24

申请人： Makoto Iwai ,  Yoshihisa Watanabe

发明人： Makoto Iwai ,  Yoshihisa Watanabe

IPC分类号： G11C16/04 ,  G11C16/02

CPC分类号： G11C16/0483 ,  G11C11/5642 ,  G11C16/26

摘要： A nonvolatile semiconductor memory includes: a memory cell unit including a plurality of memory cells having an electric charge accumulation layer and a control electrode, said memory cells being electrically connected in series; a plurality of word lines, each of which is electrically connected to said control electrode of said plurality of memory cells; a source line electrically connected to said memory cells at one end of said memory cell unit; a bit line electrically connected to said memory cells at the other end of said memory cell unit; and a control signal generation circuit, which during a data readout operation staggers a timing for selecting the word line connected to said memory cells of said memory cell unit from a timing for selecting a non-selected word line connected to a non-selected memory.

摘要翻译： 非易失性半导体存储器包括：存储单元单元，包括具有电荷累积层和控制电极的多个存储单元，所述存储单元串联电连接; 多个字线，其各自电连接到所述多个存储单元的所述控制电极; 在所述存储单元单元的一端电连接到所述存储单元的源极线; 在所述存储单元单元的另一端电连接到所述存储单元的位线; 以及控制信号生成电路，其在数据读出操作期间，从连接到未选择的存储器的未选择的字线的选择时刻开始，选择连接到所述存储单元的所述存储单元的字线的定时。

公开(公告)号：US20100135078A1

公开(公告)日：2010-06-03

申请号：US12563296

申请日：2009-09-21

申请人： Makoto Iwai ,  Hiroshi Nakamura

发明人： Makoto Iwai ,  Hiroshi Nakamura

IPC分类号： G11C16/04 ,  G11C7/10 ,  G11C16/06

CPC分类号： G11C16/3459 ,  G11C11/56 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  G11C16/26 ,  G11C16/3436 ,  G11C16/3454

摘要： A memory includes first and second select gate transistors, memory cells, a source line, a bit line, a selected word line which is connected to a selected memory cell as a target of a verify reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line, and a control circuit which classifies a threshold voltage of the selected memory cell to one of three groups by verifying which area among three area which are isolated by two values does a cell current of the selected memory cell belong, when the selected read potential is a first value.

摘要翻译： 存储器包括第一和第二选择栅极晶体管，存储器单元，源极线，位线，连接到作为验证读取的目标的所选存储单元的选定字线，连接的未选择字线 到除所选存储单元之外的未选择的存储单元，用于产生提供给所选择的字线的所选择的读取电位并产生大于所选择的读取电位的未被选择的读取电位的电位产生电路， 以及控制电路，其通过验证被选择的存储器单元的单元电流属于两个值隔离的三个区域中的哪个区域属于三个组中的一个，将选择的存储单元的阈值电压分类为三个组中的一个 当所选择的读取电位为第一值时。

公开(公告)号：US20100120950A1

公开(公告)日：2010-05-13

申请号：US12522835

申请日：2008-01-11

申请人： Takeaki Saiki ,  Makoto Iwai ,  Anil Kumar Tomar

发明人： Takeaki Saiki ,  Makoto Iwai ,  Anil Kumar Tomar

IPC分类号： C08K5/34 ,  C07F7/02

CPC分类号： C07F7/188 ,  C07F7/1804

摘要： A method for manufacturing a bis(silatranylalkyl) polysulfide by heating a bis(trialkoxysilylalkyl) polysulfide and triethanolamine in the presence of a catalytic quantity of an alkali-metal alcoholate, thus substituting all Si-bonded alkoxy groups of the bis(trialkoxysilylalkyl) polysulfide with a (OCH2CH2)3N group; a method for the preparation of a mixture of a bis(silatranylalkyl) polysulfide and a (silatranyalkyl) (trialkoxysilyl) disulfide or a mixture of a bis(silatranylalkyl) polysulfide, a (silatranylalkyl) (trialkoxysilyl) disulfide, and a bis(trialkoxysilylalkyl) polysulfide by heating a bis(trialkoxysilylalkyl) polysulfide and triethanolamine in the presence of a catalytic quantity of an alkali-metal alcoholate, thus substituting a part of Si-bonded alkoxy groups of the bis(trialkoxysilylalkyl) polysulfide with a (OCH2CH2)3N group; a mixture of a bis(silatranylalkyl) polysulfide and a (silatranylalkyl)(trialkoxysilyl) disulfide; a mixture of a bis(silatranylalkyl) polysulfide, a (silatranylalkyl)(trialkoxysilyl) disulfide, and a bis(trialkoxysilylalkyl) polysulfide; and a rubber composition containing the aforementioned mixture.

摘要翻译： 在催化量的碱金属醇化物的存在下加热双（三烷氧基甲硅烷基）多硫化物和三乙醇胺，从而将双（三烷氧基甲硅烷基烷基）多硫化物的所有Si键合的烷氧基与 （OCH 2 CH 2）3 N基团; 制备双（硅烷基烷基烷基）多硫化物和（硅烷基烷基）（三烷氧基甲硅烷基）二硫化物的混合物或双（硅烷基烷基烷基）多硫化物，（硅烷基烷基）（三烷氧基甲硅烷基）二硫化物和双（三烷氧基甲硅烷基） 通过在催化量的碱金属醇化物的存在下加热双（三烷氧基甲硅烷基）多硫化物和三乙醇胺，从而用（OCH 2 CH 2）3 N基取代双（三烷氧基甲硅烷基烷基）多硫化物的一部分Si键合的烷氧基， 双（甲硅烷基烷基）多硫化物和（硅烷基烷基烷基）（三烷氧基甲硅烷基）二硫化物的混合物; （硅烷基烷基）多硫化物，（硅烷基烷基）（三烷氧基甲硅烷基）二硫化物和双（三烷氧基甲硅烷基烷基）多硫化物的混合物; 和含有上述混合物的橡胶组合物。

公开(公告)号：US20100093157A1

公开(公告)日：2010-04-15

申请号：US12448207

申请日：2007-12-10

申请人： Shiro Yamazaki ,  Makoto Iwai ,  Takanao Shimodaira ,  Takatomo Sasaki ,  Yusuke Mori ,  Fumio Kawamura

发明人： Shiro Yamazaki ,  Makoto Iwai ,  Takanao Shimodaira ,  Takatomo Sasaki ,  Yusuke Mori ,  Fumio Kawamura

IPC分类号： H01L21/20

CPC分类号： C30B19/02 ,  C30B9/10 ,  C30B29/406 ,  H01L21/0242 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02625

摘要： A GaN single crystal 20 is grown on a crystal growth surface of a seed crystal (GaN layer 13) through the flux method in a nitrogen (N2) atmosphere at 3.7 MPa and 870° C. employing a flux mixture including Ga, Na, and Li at about 870° C. Since the back surface of the template 10 is R-plane of the sapphire substrate 11, the template 10 is readily corroded or dissolved in the flux mixture from the back surface thereof. Therefore, the template 10 is gradually dissolved or corroded from the back surface thereof, resulting in separation from the semiconductor or dissolution in the flux. When the GaN single crystal 20 is grown to a sufficient thickness, for example, about 500 μm or more, the temperature of the crucible is maintained at 850° C. to 880° C., whereby the entirety of the sapphire substrate 11 is dissolved in the flux mixture.

摘要翻译： 在氮（N 2）气氛中，在3.7MPa和870℃下，通过助熔剂法在GaN晶体生长面（GaN层13）上生长GaN单晶20，使用包含Ga，Na和 Li在约870℃。由于模板10的背面是蓝宝石衬底11的R平面，所以模板10容易被腐蚀或溶解在焊剂混合物的背面。 因此，模板10从其背面逐渐溶解或腐蚀，导致与半导体的分离或焊剂的溶解。 当GaN单晶20生长至足够的厚度，例如约500μm或更大时，坩埚的温度保持在850℃至880℃，从而整个蓝宝石衬底11溶解 在助焊剂混合物中。

公开(公告)号：US07616502B2

公开(公告)日：2009-11-10

申请号：US12108111

申请日：2008-04-23

申请人： Makoto Iwai

发明人： Makoto Iwai

IPC分类号： G11C11/34

CPC分类号： G11C16/12

摘要： A semiconductor memory device comprising: a memory cell array having memory cell units each formed by connecting a plurality of memory cells; a first and a second select gate transistors, the first select gate transistor being connected between one end of the memory cell array and a common source line, the second select gate transistor being connected between the other end of the memory cell array and bit lines; word lines acting also as control gates of the memory cells; a first select gate voltage-generating circuit for generating a first select gate voltage; a second select gate-setting circuit for setting an instructed value of a second select gate voltage; a second select gate voltage-generating circuit for generating the second select gate voltage based on the set, instructed value; a first transfer circuit for transferring the first select gate voltage generated by the first select gate voltage-generating circuit to a second select gate; a discharging circuit for discharging the first select gate voltage transferred to the second select gate; and a discharging characteristics selection circuit for selecting discharging characteristics of the discharging circuit.

摘要翻译： 一种半导体存储器件，包括：存储单元阵列，具有通过连接多个存储单元形成的存储单元单元; 第一和第二选择栅极晶体管，第一选择栅晶体管连接在存储单元阵列的一端和公共源极线之间，第二选择栅极晶体管连接在存储单元阵列的另一端和位线之间; 字线也用作存储器单元的控制栅极; 用于产生第一选择栅极电压的第一选择栅极电压产生电路; 第二选择栅极设定电路，用于设定第二选择栅极电压的指示值; 第二选择栅极电压产生电路，用于基于所设定的指示值产生第二选择栅极电压; 用于将由第一选择栅极电压产生电路产生的第一选择栅极电压转移到第二选择栅极的第一转移电路; 放电电路，用于对传送到第二选择栅极的第一选择栅极电压进行放电; 以及用于选择放电电路的放电特性的放电特性选择电路。

公开(公告)号：US20090169444A1

公开(公告)日：2009-07-02

申请号：US12225716

申请日：2007-04-05

申请人： Shiro Yamazaki ,  Makoto Iwai ,  Takanao Shimodaira ,  Takatomo Sasaki ,  Yusuke Mori ,  Fumio Kawamura

发明人： Shiro Yamazaki ,  Makoto Iwai ,  Takanao Shimodaira ,  Takatomo Sasaki ,  Yusuke Mori ,  Fumio Kawamura

IPC分类号： B01J19/00

CPC分类号： C30B9/00 ,  C30B29/403

摘要： An object of the invention is to prevent, in the flux method, diffusion of substances that constitute the atmosphere of the outer vessel into the reactor.The apparatus for producing a group III nitride based compound semiconductor, the apparatus including a reactor which maintains a group III metal and a metal differing from the group III metal in a molten state, a heating apparatus for heating the reactor, and an outer vessel for accommodating the reactor and the heating apparatus, characterized in that diffusion of substances that constitute the atmosphere of the outer vessel into the reactor is prevented.

摘要翻译： 本发明的目的是在助焊剂方法中防止构成外容器气氛的物质扩散到反应器中。 用于制造III族氮化物基化合物半导体的装置，该装置包括在熔融状态下保持III族金属和不同于III族金属的金属的反应器，用于加热反应器的加热装置和用于 容纳反应器和加热装置，其特征在于防止构成外部容器的气体的物质扩散到反应器中。