公开(公告)号：US06323139B1

公开(公告)日：2001-11-27

申请号：US09457093

申请日：1999-12-07

申请人： John T. Moore ,  Scott Jeffrey DeBoer ,  Mark Fischer ,  J. Brett Rolfson ,  Annette L. Martin ,  Ardavan Niroomand

发明人： John T. Moore ,  Scott Jeffrey DeBoer ,  Mark Fischer ,  J. Brett Rolfson ,  Annette L. Martin ,  Ardavan Niroomand

IPC分类号： H01L2131

CPC分类号： H01L21/0217 ,  G03F7/091 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/02304 ,  H01L21/02362 ,  H01L21/0274 ,  H01L21/0332 ,  H01L21/31144 ,  H01L21/312 ,  H01L21/3185

摘要： In one aspect, the invention includes a semiconductor processing method, comprising: a) providing a silicon nitride material having a surface; b) forming a barrier layer over the surface of the material, the barrier layer comprising silicon and nitrogen; and c) forming a photoresist over and against the barrier layer. In another aspect, the invention includes a semiconductor processing method, comprising: a) providing a silicon nitride material having a surface; b) forming a barrier layer over the surface of the material, the barrier layer comprising silicon and nitrogen; c) forming a photoresist over and against the barrier layer; d) exposing the photoresist to a patterned beam of light to render at least one portion of the photoresist more soluble in a solvent than an other portion, the barrier layer being an antireflective surface that absorbs light passing through the photoresist; and e) exposing the photoresist to the solvent to remove the at least one portion while leaving the other portion over the barrier layer. In yet another aspect, the invention includes a semiconductor wafer assembly, comprising: a) a silicon nitride material, the material having a surface; b) a barrier layer over the surface of the material, the barrier layer comprising silicon and nitrogen; and c) a photoresist over and against the barrier layer.

摘要翻译： 一方面，本发明包括半导体处理方法，包括：a）提供具有表面的氮化硅材料; b）在所述材料的表面上形成阻挡层，所述阻挡层包含硅和氮; 以及c）在所述阻挡层上形成光致抗蚀剂。 另一方面，本发明包括半导体处理方法，包括：a）提供具有表面的氮化硅材料; b）在所述材料的表面上形成阻挡层，所述阻挡层包含硅和氮; c）在阻挡层上形成光致抗蚀剂; d）将所述光致抗蚀剂暴露于图案化的光束以使所述光致抗蚀剂的至少一部分在溶剂中比其它部分更易溶，所述阻挡层是吸收通过所述光致抗蚀剂的光的抗反射表面; 以及e）将所述光致抗蚀剂暴露于所述溶剂以除去所述至少一个部分，同时将所述另一部分留在所述阻挡层上。 在另一方面，本发明包括半导体晶片组件，包括：a）氮化硅材料，该材料具有表面; b）在所述材料的表面上的阻挡层，所述阻挡层包含硅和氮; 以及c）在所述阻挡层上并抵靠所述阻挡层的光致抗蚀剂。

公开(公告)号：US06309973B1

公开(公告)日：2001-10-30

申请号：US09507193

申请日：2000-02-18

申请人： Mark Fischer ,  John K. Zahurak ,  Thomas M. Graettinger ,  Kunal Parekh

发明人： Mark Fischer ,  John K. Zahurak ,  Thomas M. Graettinger ,  Kunal Parekh

IPC分类号： H01L21302

CPC分类号： H01L27/10888 ,  G03F7/0757 ,  G03F7/167 ,  H01L21/76838 ,  H01L27/10852

摘要： Semiconductor processing methods of forming conductive projections and methods of increasing alignment tolerances are described. In one implementation, a conductive projection is formed over a substrate surface area and includes an upper surface and a side surface joined therewith to define a corner region. The corner region of the conductive projection is subsequently beveled to increase an alignment tolerance relative thereto. In another implementation, a conductive plug is formed over a substrate node location between a pair of conductive lines and has an uppermost surface. Material of the conductive plug is unevenly removed to define a second uppermost surface, at least a, portion of which is disposed elevationally higher than a conductive line. In one aspect, conductive plug material can be removed by facet etching the conductive plug. In another aspect, conductive plug material is unevenly doped with dopant, and conductive plug material containing greater concentrations of dopant is etched at a greater rate than plug material containing lower concentrations of dopant.

摘要翻译： 描述形成导电突起的半导体加工方法和增加对准公差的方法。 在一个实施方案中，导电突起形成在衬底表面区域上，并且包括与其连接的上表面和侧表面以限定拐角区域。 导电突起的角区域随后被倒角以增加相对于其的对准公差。 在另一实施方案中，导电插塞形成在一对导线之间的衬底节点位置之上并且具有最上表面。 导电插塞的材料被不均匀地移除以限定第二最上表面，其中至少一部分的表面布置在高于导电线的高度上。 在一个方面，可以通过刻蚀导电插塞去除导电插塞材料。 在另一方面，导电插塞材料用掺杂剂不均匀掺杂，并且以比含有较低浓度掺杂剂的插塞材料更大的速率蚀刻含有较大浓度掺杂剂的导电插塞材料。

公开(公告)号：US6010941A

公开(公告)日：2000-01-04

申请号：US112629

申请日：1998-07-09

申请人： Mark Fischer ,  Mark Jost ,  Kunal Parekh

发明人： Mark Fischer ,  Mark Jost ,  Kunal Parekh

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L21/20

CPC分类号： H01L27/10852 ,  H01L28/40 ,  Y10S148/02

摘要： A semiconductor processing method of forming a stacked container capacitor includes, a) providing a pair of spaced conductive runners relative to a substrate, the conductive runners respectively having electrically insulative sidewall spacers and an electrically insulative cap, the caps having respective outer surfaces; b) providing a node between the runners to which electrical connection to a capacitor is to be made; c) providing an electrically conductive pillar in electrical connection with the node, the pillar projecting outwardly relative to the node between the runners and having a first outer surface positioned outwardly of both runner caps, the pillar completely filling the space between the pair of runners at the location where the pillar is located; d) providing an insulating dielectric layer outwardly of the caps and the conductive pillar; e) etching a container opening through the insulating dielectric layer to outwardly expose the conductive pillar first outer surface; f) etching the exposed conductive pillar to define a pillar second outer surface which is closer to the node than the pillar first outer surface and to deepen the container opening; g) providing an electrically conductive storage node container layer within the container opening over the second outer conductive pillar surface; h) providing a capacitor dielectric layer over the capacitor storage node layer; and i) providing an electrically conductive outer capacitor plate over the capacitor dielectric layer. Such a capacitor construction is also disclosed.

摘要翻译： 形成层叠容器电容器的半导体处理方法包括：a）相对于衬底提供一对隔开的导电流道，所述导电流道分别具有电绝缘侧壁间隔件和电绝缘帽，所述帽具有相应的外表面; b）在要与电容器进行电连接的流道之间提供节点; c）提供与所述节点电连接的导电柱，所述柱相对于所述流道之间的节点向外突出，并且具有位于两个流道盖之外的第一外表面，所述柱完全填充所述一对流道之间的空间， 支柱所在的位置; d）在盖和导电柱之外提供绝缘介电层; e）蚀刻通过所述绝缘介电层的容器开口以向外暴露所述导电柱第一外表面; f）蚀刻暴露的导电柱以限定比第一外表面更靠近节点的支柱第二外表面并加深容器开口; g）在第二外导电柱表面之上的容器开口内提供导电存储节点容器层; h）在所述电容器存储节点层上提供电容器介电层; 以及i）在所述电容器介电层上方提供导电的外部电容器板。 还公开了这种电容器结构。

公开(公告)号：US5985771A

公开(公告)日：1999-11-16

申请号：US57152

申请日：1998-04-07

申请人： John T. Moore ,  Scott J. DeBoer ,  Mark Fischer

发明人： John T. Moore ,  Scott J. DeBoer ,  Mark Fischer

IPC分类号： H01L21/318 ,  H01L21/32 ,  H01L21/762

CPC分类号： H01L21/3185 ,  H01L21/32 ,  H01L21/76202

摘要： In one aspect, the invention includes a method of semiconductive wafer processing comprising forming a silicon nitride layer over a surface of a semiconductive wafer, the silicon nitride layer comprising at least two portions, one of said at least two portions generating a compressive force against the other of the at least two portions, and the other of the at least two portions generating a tensile force against the one of the at least two portions. In another aspect, the invention includes a method of reducing stress on semiconductive wafer, the semiconductive wafer having a pair of opposing surfaces and having more silicon nitride over one of the opposing surfaces than over the other of the opposing surfaces, the method comprising providing the silicon nitride over the one of the opposing surfaces to comprise a first portion, a second portion and a third portion, the first, second and third portions being elevationally displaced relative to one another, the second portion being between the first and third portions, the second portion having a greater stoichiometric amount of silicon than the first and third portions, the semiconductive wafer being subjected to less stress than if the silicon nitride over the one of the opposing surfaces had a constant stoichiometric amount of silicon throughout its thickness. In yet other aspects, the invention includes semiconductive wafer assemblies.

公开(公告)号：US20160350091A1

公开(公告)日：2016-12-01

申请号：US14722351

申请日：2015-05-27

申请人： Prakash Khot ,  Mark Fischer ,  Daniel Philip Arcari

发明人： Prakash Khot ,  Mark Fischer ,  Daniel Philip Arcari

IPC分类号： G06F9/45 ,  G06F9/44

CPC分类号： G06F8/51 ,  G06F3/06 ,  G06F8/315 ,  G06F8/35 ,  G06F8/36 ,  G06F9/44505

摘要： Computer implemented techniques for storage management include transforming file instances using a modeling language platform that includes a language grammar and a set of language processing rules to transform instances of an entity written in the language grammar into a platform independent code and artifact files and auto-generating by the modeling language platform code to recognize and process input in a given language to deconstruct file instances into pieces that allow further discrete operations to be performed on the file instances.

摘要翻译： 用于存储管理的计算机实现技术包括使用包括语言语法和一组语言处理规则的建模语言平台来转换文件实例，以将以语言语法编写的实体的实例转换为独立于平台的代码和工件文件和自动生成 通过建模语言平台代码来识别和处理给定语言中的输入，以将文件实例解构为允许对文件实例执行进一步离散操作的部分。

公开(公告)号：US20120328369A1

公开(公告)日：2012-12-27

申请号：US13516329

申请日：2010-11-29

申请人： Heiko Hoeft ,  Holger Gutschmidt ,  Andreas Diener ,  Andreas Artus ,  Mark Fischer ,  Matthias Klug

发明人： Heiko Hoeft ,  Holger Gutschmidt ,  Andreas Diener ,  Andreas Artus ,  Mark Fischer ,  Matthias Klug

IPC分类号： E21D11/38 ,  F16J15/06

CPC分类号： E21D11/385

摘要： A sealing arrangement for shaft and tunnel constructions. The sealing of gaps between components of shaft and tunnel constructions is improved, in particular if the components are misaligned. For this purpose a) the sealing arrangement (1) comprises at least two components (2), which lie against each other at butt sides (3) so as to form a gap (4), b) the components (2) have an elastic sealing profile (5) on each butt side (3), and c) the sealing profiles (5) of the butt sides (3) that lie against each other lie against each other on a contact plane (6) and bridge the gap (4) in a sealing manner. The sealing profiles (5) have areas (7, 8) of different hardness arranged in alternation in the transverse direction (9) perpendicular to the respective profile longitudinal plane (10), the sealing profiles (5) of butt sides (3) that lie against each other differing from each other in the arrangement of the areas (7, 8) of different hardness in the transverse direction (9).

摘要翻译： 轴和隧道结构的密封装置。 改进了轴和组件之间的间隙的密封，特别是如果部件不对准。 为此目的a）密封装置（1）包括至少两个部件（2），它们在对接面（3）处彼此相对以形成间隙（4），b）部件（2）具有 每个对接侧（3）上的弹性密封型材（5），以及c）彼此相对的对接面（3）的密封型材（5）在接触平面（6）上彼此抵靠并桥接间隙 （4）。 密封型材（5）具有垂直于相应轮廓纵向平面（10）的横向（9）交替地布置的具有不同硬度的区域（7,8），对接侧面（3）的密封型材（5） 在横向（9）上具有不同硬度的区域（7,8）的布置彼此不同。

公开(公告)号：US20120238061A1

公开(公告)日：2012-09-20

申请号：US13485892

申请日：2012-05-31

申请人： Mark Fischer ,  Sanh D. Tang

发明人： Mark Fischer ,  Sanh D. Tang

IPC分类号： H01L21/336

CPC分类号： H01L27/10876 ,  H01L21/823425 ,  H01L21/823487 ,  H01L27/2454 ,  H01L29/0653 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/66666 ,  H01L29/7827 ,  H01L45/06 ,  H01L45/1233

摘要： Some embodiments include methods of forming vertical transistors. A construction may have a plurality of spaced apart fins extending upwardly from a semiconductor substrate. Each of the fins may have vertical transistor pillars, and each of the vertical transistor pillars may have a bottom source/drain region location, a channel region location over the bottom source/drain region location, and a top source/drain region location over the channel region location. Electrically conductive gate material may be formed along the fins while using oxide within spaces along the bottoms of the fins to offset the electrically conductive gate material to be above the bottom source/drain region locations of the vertical transistor pillars. The oxide may be an oxide which etches at a rate of at least about 100 Å/minute with dilute HF at room temperature. In some embodiments the oxide may be removed after the electrically conductive gate material is formed.

摘要翻译： 一些实施例包括形成垂直晶体管的方法。 结构可以具有从半导体衬底向上延伸的多个间隔开的翅片。 每个鳍片可以具有垂直的晶体管柱，并且每个垂直晶体管柱可以具有底部源极/漏极区域位置，在底部源极/漏极区域位置上方的沟道区域位置，以及顶部源极/漏极区域 渠道区域位置。 导电栅极材料可以沿着鳍片形成，同时沿着鳍状物的底部在空间内使用氧化物以将导电栅极材料偏移到垂直晶体管柱的底部源极/漏极区域的上方。 氧化物可以是在室温下用稀释HF以至少约100埃/分钟的速率蚀刻的氧化物。 在一些实施例中，可以在形成导电栅极材料之后去除氧化物。

公开(公告)号：US08154081B2

公开(公告)日：2012-04-10

申请号：US13017854

申请日：2011-01-31

申请人： Mark Fischer ,  T. Earl Allen ,  H. Montgomery Manning

发明人： Mark Fischer ,  T. Earl Allen ,  H. Montgomery Manning

IPC分类号： H01L27/12

CPC分类号： H01L29/785 ,  H01L29/66818 ,  H01L29/7853 ,  Y10S438/947

摘要： A process may include first etching a trench isolation dielectric through a dielectric hard mask that abuts the sidewall of a fin semiconductor. The first etch can be carried out to expose at least a portion of the sidewall, causing the dielectric hard mask to recede to a greater degree in the lateral direction than the vertical direction. The process may include second etching the fin semiconductor to achieve a thinned semiconductor fin, which has receded beneath the shadow of the laterally receded hard mask. The thinned semiconductor fin may have a characteristic dimension that can exceed photolithography limits. Electronic devices may include the thinned semiconductor fin as part of a field effect transistor.

摘要翻译： 工艺可以包括首先通过与散热片半导体的侧壁邻接的电介质硬掩模蚀刻沟槽隔离电介质。 可以执行第一蚀刻以暴露侧壁的至少一部分，使得电介质硬掩模在横向方向上比垂直方向更大程度地退回。 该方法可以包括第二蚀刻鳍式半导体以实现减薄的半导体鳍片，其已经在横向后退的硬掩模的阴影之下退化。 减薄的半导体鳍片可以具有可超过光刻极限的特征尺寸。 电子器件可以包括作为场效应晶体管的一部分的变薄的半导体鳍片。

公开(公告)号：US20120061740A1

公开(公告)日：2012-03-15

申请号：US13302090

申请日：2011-11-22

申请人： Kevin J. Torek ,  Mark Fischer ,  Robert J. Hanson

发明人： Kevin J. Torek ,  Mark Fischer ,  Robert J. Hanson

IPC分类号： H01L27/06 ,  H01L29/78

CPC分类号： H01L29/7851 ,  H01L27/10808 ,  H01L27/10826 ,  H01L27/10879 ,  H01L29/66795 ,  H01L29/7853 ,  H01L29/7854

摘要： Novel etch techniques are provided for shaping silicon features below the photolithographic resolution limits. FinFET devices are defined by recessing oxide and exposing a silicon protrusion to an isotropic etch, at least in the channel region. In one implementation, the protrusion is contoured by a dry isotropic etch having excellent selectivity, using a downstream microwave plasma etch.

摘要翻译： 提供了新颖的蚀刻技术，用于在低于光刻分辨率极限的条件下成形硅特征。 FinFET器件通过凹陷氧化物和至少在沟道区域中将硅突起暴露于各向同性蚀刻来限定。 在一个实施方案中，使用下游微波等离子体蚀刻，通过具有优异选择性的干各向同性蚀刻来形成突起。

公开(公告)号：US20120052640A1

公开(公告)日：2012-03-01

申请号：US12872705

申请日：2010-08-31

申请人： Mark Fischer ,  Sanh D. Tang

发明人： Mark Fischer ,  Sanh D. Tang

IPC分类号： H01L21/336

CPC分类号： H01L27/10876 ,  H01L21/823425 ,  H01L21/823487 ,  H01L27/2454 ,  H01L29/0653 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/66666 ,  H01L29/7827 ,  H01L45/06 ,  H01L45/1233

摘要： Some embodiments include methods of forming vertical transistors. A construction may have a plurality of spaced apart fins extending upwardly from a semiconductor substrate. Each of the fins may have vertical transistor pillars, and each of the vertical transistor pillars may have a bottom source/drain region location, a channel region location over the bottom source/drain region location, and a top source/drain region location over the channel region location. Electrically conductive gate material may be formed along the fins while using oxide within spaces along the bottoms of the fins to offset the electrically conductive gate material to be above the bottom source/drain region locations of the vertical transistor pillars. The oxide may be an oxide which etches at a rate of at least about 100 Å/minute with dilute HF at room temperature. In some embodiments the oxide may be removed after the electrically conductive gate material is formed.

摘要翻译： 一些实施例包括形成垂直晶体管的方法。 结构可以具有从半导体衬底向上延伸的多个间隔开的翅片。 每个鳍片可以具有垂直的晶体管柱，并且每个垂直晶体管柱可以具有底部源极/漏极区域位置，在底部源极/漏极区域位置上方的沟道区域位置，以及顶部源极/漏极区域 渠道区域位置。 导电栅极材料可以沿着鳍片形成，同时沿着鳍状物的底部在空间内使用氧化物以将导电栅极材料偏移到垂直晶体管柱的底部源极/漏极区域的上方。 氧化物可以是在室温下用稀释HF以至少约100埃/分钟的速率蚀刻的氧化物。 在一些实施例中，可以在形成导电栅极材料之后去除氧化物。