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    Integrated semiconductor memory
    61.
    发明授权
    Integrated semiconductor memory 有权
    集成半导体存储器

    公开(公告)号：US6125073A

    公开(公告)日：2000-09-26

    申请号：US391717

    申请日：1999-09-08

    Applicant: Thoai-Thai Le ,  Jurgen Lindolf ,  Eckhard Brass ,  Martin Brox

    Inventor： Thoai-Thai Le ,  Jurgen Lindolf ,  Eckhard Brass ,  Martin Brox

    IPC: G11C11/407 ,  G11C5/14 ,  G11C8/08 ,  G11C11/401 ,  G11C8/00

    CPC classification number: G11C5/14 ,  G11C8/08

    Abstract: In an integrated semiconductor memory having a memory cell array divided into memory banks, supply potentials with high drive capability are applied to the memory banks only if the respective memory bank is activated for access to a memory cell. For this purpose a supply voltage assigned to the respective memory bank is controlled by the same address signal as the memory bank. The supply voltage sources generate a word line potential, a bit line potential or a substrate potential. As a result, a power loss is reduced.

    Abstract translation: 在具有划分为存储体的存储单元阵列的集成半导体存储器中，只有当相应的存储体被激活以访问存储单元时，具有高驱动能力的电源才被施加到存储体。 为此，分配给相应存储体的电源电压由与存储体相同的地址信号控制。 电源电压源产生字线电位，位线电位或衬底电位。 结果，功率损耗降低。

    Apparatus for controlling circuit response during power-up
    62.
    发明授权
    Apparatus for controlling circuit response during power-up 有权
    用于控制上电期间电路响应的装置

    公开(公告)号：US5995436A

    公开(公告)日：1999-11-30

    申请号：US187153

    申请日：1998-11-06

    Applicant: Martin Brox ,  Franz Freimuth ,  Mike Killian ,  Naokazu Miyawaki ,  Thilo Schaffroth

    Inventor： Martin Brox ,  Franz Freimuth ,  Mike Killian ,  Naokazu Miyawaki ,  Thilo Schaffroth

    IPC: G11C11/41 ,  G11C5/14 ,  G11C7/20 ,  G11C7/22 ,  G11C11/401

    CPC classification number: G11C7/22 ,  G11C5/143 ,  G11C7/20

    Abstract: A circuit embodying the invention includes a gating circuit responsive to a first control signal and to a second externally supplied control signal having an active state and an inactive state. The first control signal is produced by a power supply circuit which is responsive to the application of an externally supplied operating voltage for producing an "internal" operating voltage and which produces the first control signal having an active state when the internal operating voltage reaches a predetermined value. The gating circuit has an output for producing a third control signal which is enabling only if the second control signal goes from its inactive state to its active state when the first control signal is already in, and remains in, its active state. The gating circuit prevents a chip from operating in an unintended mode at power-up.

    Abstract translation: 体现本发明的电路包括响应于第一控制信号的门控电路和具有活动状态和非活动状态的第二外部提供的控制信号。 第一控制信号由电源电路产生，电源电路响应于施加外部提供的工作电压以产生“内部”工作电压，并且当内部工作电压达到预定的工作电压时产生具有有效状态的第一控制信号 值。 门控电路具有用于产生第三控制信号的输出，该第三控制信号仅在第一控制信号已经处于其活动状态时才能使第二控制信号从其无效状态变为其活动状态。 门控电路可防止芯片在上电时以非预期模式运行。

    Voltage regulation system
    64.
    发明授权
    Voltage regulation system 有权
    电压调节系统

    公开(公告)号：US07965066B2

    公开(公告)日：2011-06-21

    申请号：US10585151

    申请日：2004-11-23

    Applicant: Martin Brox

    Inventor： Martin Brox

    IPC: G05F1/00 ,  G05F3/16 ,  G05F3/20

    CPC classification number: G05F1/465

    Abstract: One aspect of the invention relates to a voltage regulation process as well as to a voltage regulation system. A first voltage, present at an input of the voltage regulating system, is changed into a second voltage, which can be tapped at an output of the voltage regulation system, with a first device for generating an essentially constant voltage from the first voltage, or a voltage derived from it. A further device is provided for generating a further voltage from the first voltage or a voltage derived from it, in particular a voltage which can be higher than the voltage generated by the first device.

    Abstract translation: 本发明的一个方面涉及电压调节过程以及电压调节系统。 存在于电压调节系统的输入处的第一电压被改变成可以在电压调节系统的输出处被抽头的第二电压，第一电压用于从第一电压产生基本上恒定的电压，或 来自它的电压。 提供了另外的装置，用于从第一电压或从其导出的电压产生另外的电压，特别是可以高于由第一装置产生的电压的电压。

    DIGITAL DATA INVERSION FLAG GENERATOR CIRCUIT
    66.
    发明申请
    DIGITAL DATA INVERSION FLAG GENERATOR CIRCUIT 有权
    数字数据逆变器发生器电路

    公开(公告)号：US20100052729A1

    公开(公告)日：2010-03-04

    申请号：US12201876

    申请日：2008-08-29

    Applicant: Martin Brox ,  Ronny Schneider

    Inventor： Martin Brox ,  Ronny Schneider

    IPC: H03K19/00 ,  G11C11/34

    CPC classification number: G06F13/4239

    Abstract: An integrated circuit includes an array of memory cells and a digital flag generator circuit configured to generate a data inversion flag based on whether a number of logical zero bits contained in a data word to be transmitted from the memory cells is greater than a threshold number. The digital flag generator circuit includes a first digital stage including a first plurality of binary logic circuits. Each of the binary logic circuits is configured to receive a subset of the data word.

    Abstract translation: 集成电路包括存储器单元阵列和数字标志发生器电路，该数字标志发生器电路被配置为基于从存储器单元发送的数据字中包含的逻辑零比特数是否大于阈值来生成数据反转标志。 数字标志发生器电路包括包括第一多个二进制逻辑电路的第一数字级。 每个二进制逻辑电路被配置为接收数据字的子集。

    Integrated semiconductor memory device with clock generation
    67.
    发明授权
    Integrated semiconductor memory device with clock generation 失效
    具有时钟发生的集成半导体存储器件

    公开(公告)号：US07505359B2

    公开(公告)日：2009-03-17

    申请号：US11749226

    申请日：2007-05-16

    Applicant: Martin Brox

    Inventor： Martin Brox

    IPC: G11C8/00

    CPC classification number: G11C7/22 ,  G11C5/143 ,  G11C7/222 ,  G11C11/4074 ,  G11C11/4076 ,  G11C2207/2227

    Abstract: A memory device can be operated in a first operating state and a second operating state, where read access to memory cells can be performed in the first operating state. The memory device includes an activatable clock generator circuit to generate a clock signal. The clock generator circuit can be operated in an activated state, in which it generates the clock signal, and in a deactivated state, in which generation of the clock signal is suppressed. The activatable clock generator circuit is operated in the activated state at a time period after changeover of the memory device from the first operating state to the second operating state, and is changed over from the activated state to the deactivated state no later than after the period has elapsed.

    Abstract translation: 存储器件可以在第一操作状态和第二操作状态下操作，其中可以在第一操作状态下执行对存储器单元的读访问。 该存储器件包括可产生时钟信号的可激活时钟发生器电路。 时钟发生器电路可以在其产生时钟信号的激活状态下工作，并且在停止状态中抑制时钟信号的产生。 可激活时钟发生器电路在存储器件从第一操作状态切换到第二操作状态之后的时间段处于激活状态下操作，并且不迟于该周期之后从激活状态切换到去激活状态 已经过去了

    Memory circuit, a dynamic random access memory, a system comprising a memory and a floating point unit and a method for storing digital data
    69.
    发明申请
    Memory circuit, a dynamic random access memory, a system comprising a memory and a floating point unit and a method for storing digital data 失效
    存储器电路，动态随机存取存储器，包括存储器和浮点单元的系统以及用于存储数字数据的方法

    公开(公告)号：US20080062743A1

    公开(公告)日：2008-03-13

    申请号：US11530858

    申请日：2006-09-11

    Applicant: Peter Mayer ,  Wolfgang Spirkl ,  Markus Balb ,  Christoph Bilger ,  Martin Brox ,  Thomas Hein ,  Michael Richter

    Inventor： Peter Mayer ,  Wolfgang Spirkl ,  Markus Balb ,  Christoph Bilger ,  Martin Brox ,  Thomas Hein ,  Michael Richter

    IPC: G11C11/24

    CPC classification number: G11C7/16 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/1078 ,  G11C7/1096 ,  G11C11/4085 ,  G11C11/4096

    Abstract: A memory circuit comprises a D/A converter connected with an input/output circuit and with a writing circuit, wherein the D/A converter converts a digital data with at least two digital bits received from the input/output circuit to one analog value and forwards the analog value to the writing circuit, wherein the digital data is at least a part of a floating point number, wherein the writing circuit writes the analog value in at least one selected memory cell, and an A/D converter connected with a reading circuit and with the input/output circuit, wherein the reading circuit reads an analog value from a selected memory cell and forwards the analog value to the A/D converter, wherein the A/D converter converts the analog value to digital data, and wherein the A/D converter forwards the digital data to the input/output circuit. Furthermore, a method is provided for reading data from at least one memory cell of a memory, wherein an analog value is read from the memory cell and the analog value is corrected according to a correction factor representing a storage time the analog value was stored and wherein the corrected analog value is converted to digital data.

    Abstract translation: 存储电路包括与输入/输出电路和写入电路连接的D / A转换器，其中D / A转换器将具有从输入/输出电路接收的至少两个数字位的数字数据转换成一个模拟值， 将模拟值转发到写入电路，其中数字数据是浮点数的至少一部分，其中写入电路将模拟值写入至少一个选择的存储单元，以及与读取器连接的A / D转换器 电路和输入/输出电路，其中读取电路从所选择的存储器单元读取模拟值并将模拟值转发到A / D转换器，其中A / D转换器将模拟值转换为数字数据，其中 A / D转换器将数字数据转发到输入/输出电路。 此外，提供一种用于从存储器的至少一个存储单元读取数据的方法，其中从存储器单元读取模拟值，并且根据表示存储模拟值的存储时间的校正因子来校正模拟值，以及 其中所述经修正的模拟值被转换为数字数据。

    Electronic Circuit Arrangement With Active Control During The Reception Of A Received Electrical Signal
    70.
    发明申请
    Electronic Circuit Arrangement With Active Control During The Reception Of A Received Electrical Signal 审中-公开
    在接收电信号期间主动控制的电子电路布置

    公开(公告)号：US20080061862A1

    公开(公告)日：2008-03-13

    申请号：US11664011

    申请日：2005-10-19

    Applicant: Rainer Bartenschlager ,  Martin Brox ,  Thomas Hein ,  Ullrich Menczigar

    Inventor： Rainer Bartenschlager ,  Martin Brox ,  Thomas Hein ,  Ullrich Menczigar

    IPC: H03K3/26

    CPC classification number: H03F1/30 ,  H03F2200/78 ,  H03K5/2481

    Abstract: The invention creates an electronic circuit arrangement for receiving a received electrical signal (101) with a first receiving device (100), a second receiving device (200) and a comparator unit (301) for comparing a second signal difference (207), output by the second receiving device (200), with a target value signal (303) and for outputting a control signal (305) in dependence on the comparison, wherein the control signal (305) controls both the first receiving device (100) and the second receiving device (200) into a respective operating point in such a manner that the amplified second signal difference (207) is held at a level of the target value signal (303) and a first signal difference (107) output from the first receiving device (100) supplies with high accuracy a measure of the received signal (101) with respect to a predetermined reference signal (103).

    Abstract translation: 本发明创建一个电子电路装置，用于利用第一接收装置（100），第二接收装置（200）和比较器装置（301）来接收接收的电信号（101），用于比较第二信号差（207），输出 通过第二接收装置（200）与目标值信号（303）相对应地输出控制信号（305），其中控制信号（305）控制第一接收装置（100）和 第二接收装置（200）以放大的第二信号差（207）保持在目标值信号（303）的电平和从第一接收（303）输出的第一信号差（107）的方式进入相应的工作点 设备（100）以高精度提供相对于预定参考信号（103）的接收信号（101）的测量。

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