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    Flash memory architecture with separate storage of overhead and user data
    64.
    发明授权
    Flash memory architecture with separate storage of overhead and user data 有权
    闪存体系结构，分开存储开销和用户数据

    公开(公告)号：US07552274B2

    公开(公告)日：2009-06-23

    申请号：US11595730

    申请日：2006-11-08

    申请人： Petro Estakhri ,  Siamack Nemazie

    发明人： Petro Estakhri ,  Siamack Nemazie

    IPC分类号： G06F12/02 ,  G11C16/00

    CPC分类号： G06F3/0605 ,  G06F3/0616 ,  G06F3/0631 ,  G06F3/064 ,  G06F3/0647 ,  G06F3/0679 ,  G06F12/0246 ,  G06F12/1009 ,  G06F2212/1036 ,  G06F2212/214 ,  G06F2212/657 ,  G06F2212/7201 ,  G06F2212/7204 ,  G06F2212/7211 ,  G11C16/102

    摘要： A flash memory system segregates overhead data from user data so that overhead data may be addressed, programmed and erased independently from user data. The non-volatile memory medium of a flash memory system is mapped into a plurality of separate and separately addressable memory blocks that are independently programmable and independently erasable, including Dedicated Overhead Blocks and Dedicated Data Blocks. The Dedicated Overhead Blocks are mapped according to a plurality of distinguishably addressable segments. User Data defined by a VLBA is stored in a Dedicated Data Block within the flash memory. Successively generated sets of Overhead Data are stored in respective segments in the Dedicated Overhead Blocks. When a Dedicated Overhead Block is designated for erasure, any current overhead segments are consolidated and moved to a new Dedicated Overhead Block., and the full or obsolete block is erased.

    摘要翻译： 闪存系统将开销数据与用户数据隔离开，从而可以独立于用户数据寻址，编程和擦除开销数据。 闪速存储器系统的非易失性存储介质被映射到独立且可单独地寻址的存储器块，其独立地可编程并且可独立地可擦除，包括专用开销块和专用数据块。 专用开销块根据多个可区分地寻址的段映射。 由VLBA定义的用户数据存储在闪存中的专用数据块中。 连续生成的开销数据集存储在专用开销块中的相应段中。 当专用的开销块被指定用于擦除时，任何当前的开销段都被合并并移动到一个新的专用开销块，并且完全或过时的块被擦除。

    Route aware Serial Advanced Technology Attachment (SATA) Switch
    65.
    发明授权
    Route aware Serial Advanced Technology Attachment (SATA) Switch 有权
    路由感知串行高级技术附件（SATA）开关

    公开(公告)号：US07539797B2

    公开(公告)日：2009-05-26

    申请号：US10775523

    申请日：2004-02-09

    申请人： Siamack Nemazie ,  Andrew Hyonil Chong

    发明人： Siamack Nemazie ,  Andrew Hyonil Chong

    IPC分类号： G06F13/12 ,  G06F13/38

    CPC分类号： G06F13/4022

    摘要： A switch is coupled between a plurality of host units and a device for routing frame information therebetween. The switch includes a first serial advanced technology attachment (ATA) port including a first host task file that is responsive to a non-data frame information structure (FIS) from a first host unit. The switch further includes a second serial ATA port including a second host task file that is responsive to a non-data FIS from a second host unit. The switch further includes a third serial ATA port that is responsive to a non-data FIS from a device and further includes an arbitration and control circuit for selecting one of the first host or second host units to concurrently access the device, through the switch, by accepting non-data FIS, from either of the first or second host units, at any given time, including when the device is not in an idle state.

    摘要翻译： 交换机耦合在多个主机单元和用于在其间路由帧信息的设备。 交换机包括第一串行高级技术附件（ATA）端口，其包括响应于来自第一主机单元的非数据帧信息结构（FIS）的第一主机任务文件。 交换机还包括第二串行ATA端口，其包括响应于来自第二主机单元的非数据FIS的第二主机任务文件。 该交换机还包括响应来自设备的非数据FIS的第三串行ATA端口，并且还包括仲裁和控制电路，用于通过交换机选择第一主机或第二主机单元中的一个并发访问设备， 通过在任何给定的时间，包括当设备不处于空闲状态时从第一或第二主机单元中的任一个接收非数据FIS。

    Serial Advanced Technology Attachment (SATA) switch
    66.
    发明授权
    Serial Advanced Technology Attachment (SATA) switch 有权
    串行高级技术附件（SATA）开关

    公开(公告)号：US07523235B2

    公开(公告)日：2009-04-21

    申请号：US10775488

    申请日：2004-02-09

    申请人： Sam Nemazie ,  Shiang-Jyh Chang ,  Young-Ta Wu ,  Siamack Nemazie ,  Andrew Hyonil Chong

    发明人： Sam Nemazie ,  Shiang-Jyh Chang ,  Young-Ta Wu ,  Siamack Nemazie ,  Andrew Hyonil Chong

    IPC分类号： G06F13/12 ,  G06F13/38

    CPC分类号： G06F13/4022

    摘要： A switch is coupled between a plurality of host units and a device for communicating therebetween. Included is a first serial advanced technology attachment (SATA) port, a second SATA port, and a third SATA port. The first SATA port includes a first host task file coupled to a first host unit, and the first host task file is responsive to commands sent by the first host unit to the device. The second SATA port includes a second host task file coupled to a second host unit, and the second host task file is responsive to commands sent by the second host unit to the device. An arbitration control circuit is coupled to the SATA ports, and selects from the first and second hosts to concurrently access the device, through the switch, accepting commands from either host units at any time, including when the device is not idle.

    摘要翻译： 开关耦合在多个主机单元和用于在它们之间通信的装置。 包括第一个串行高级技术附件（SATA）端口，第二个SATA端口和第三个SATA端口。 第一SATA端口包括耦合到第一主机单元的第一主机任务文件，并且第一主机任务文件响应于由第一主机单元发送到设备的命令。 第二SATA端口包括耦合到第二主机单元的第二主机任务文件，并且第二主机任务文件响应于由第二主机单元发送到设备的命令。 仲裁控制电路耦合到SATA端口，并且通过交换机从第一和第二主机中选择同时访问设备，在任何时候接收来自主机单元的命令，包括何时设备不空闲。

    ERROR SCANNING IN FLASH MEMORY
    67.
    发明申请
    ERROR SCANNING IN FLASH MEMORY 有权
    闪存中的错误扫描

    公开(公告)号：US20090055697A1

    公开(公告)日：2009-02-26

    申请号：US11843466

    申请日：2007-08-22

    申请人： William Henry Radke ,  Peter Sean Feeley ,  Siamack Nemazie

    发明人： William Henry Radke ,  Peter Sean Feeley ,  Siamack Nemazie

    IPC分类号： G06F11/00

    CPC分类号： G06F11/006 ,  G06F11/106

    摘要： Various embodiments include methods, apparatus, and systems to scan at least a portion of a memory device when a condition for scanning is met. The condition may be dependent on one or more of a number of read operations, a number of write operations, time, and others. Other embodiments including additional methods, apparatus, and systems are disclosed.

    摘要翻译： 各种实施例包括当满足扫描条件时扫描存储器件的至少一部分的方法，装置和系统。 条件可以取决于多个读取操作，多个写入操作，时间等中的一个或多个。 公开了包括附加方法，装置和系统的其它实施例。

    Semiconductor memory device for mass storage block access applications
    70.
    发明授权
    Semiconductor memory device for mass storage block access applications 失效
    用于大容量存储块存取应用的半导体存储器件

    公开(公告)号：US5864568A

    公开(公告)日：1999-01-26

    申请号：US885320

    申请日：1997-06-30

    申请人： Siamack Nemazie

    发明人： Siamack Nemazie

    IPC分类号： G06F3/06 ,  G06F11/10 ,  G11C7/10 ,  G06F13/00 ,  G06F13/12

    CPC分类号： G06F3/0613 ,  G06F3/0656 ,  G06F3/0679 ,  G11C7/103 ,  G06F11/1068

    摘要： In storage subsystems such as winchester disk, blocks of sequential data corresponding to sectors are concurrently accessed by the disk and the host. Semiconductor memory devices for storing block data are often utilized as storage location for sectors of data read or written to the disk and the host. Application of a semiconductor memory which increases the effective transfer rate of the system is highly desirable particularly in disk storage systems. A semiconductor memory for use in disk storage applications where information is transferred in blocks of data is hereby disclosed. Specifically, the memory includes a main memory configured as a random access memory array having rows and columns, each row having a plurality of n-bit words, a secondary memory having a data register file, first and second parallel-by-bit interfaces and a transferring circuit for transferring data between the main and secondary memories. Access to the main memory through a first interface is achieved independently of accesses to the secondary memory through a second interface thereby allowing concurrent accesses. Accordingly, concurrent and independent semiconductor memory accesses by any two utilization devices located externally to the memory such as a host, a disk sequencer, an ECC logic or a microcontroller are performed without corruption of the data. Further included in the secondary memory is a mask register file for maintaining the integrity of adjacent blocks of data when a block or sector of data having more words than the number of words in a row of the main memory is affected.

    摘要翻译： 在诸如温彻斯特磁盘的存储子系统中，对应于扇区的顺序数据块由磁盘和主机同时访问。 用于存储块数据的半导体存储器件通常用作读取或写入盘和主机的扇区的存储位置。 提高系统有效传输速率的半导体存储器的应用是非常需要的，特别是在磁盘存储系统中。 特此公开了一种用于在数据块传送信息的磁盘存储应用中的半导体存储器。 具体地说，存储器包括被配置为具有行和列的随机存取存储器阵列的主存储器，每行具有多个n位字，具有数据寄存器文件的辅存储器，第一和第二并行比特接口以及 用于在主存储器和次存储器之间传送数据的传送电路。 独立于通过第二接口对辅助存储器的访问实现通过第一接口访问主存储器，从而允许并发访问。 因此，在不破坏数据的情况下，执行位于诸如主机，磁盘定序器，ECC逻辑或微控制器之类的存储器外部的任何两个利用装置的并发且独立的半导体存储器访问。 辅助存储器中还包括一个掩码寄存器文件，用于当具有比主存储器的一行中的字数更多的字数据的数据块或扇区受到影响时，保持相邻数据块的完整性。