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    Method and system for reducing the number of connections between a plurality of semiconductor devices
    61.
    发明授权
    Method and system for reducing the number of connections between a plurality of semiconductor devices 失效
    用于减少多个半导体器件之间的连接数目的方法和系统

    公开(公告)号：US5625563A

    公开(公告)日：1997-04-29

    申请号：US370210

    申请日：1995-01-09

    申请人： Michael D. Rostoker ,  Scott A. Macomber

    发明人： Michael D. Rostoker ,  Scott A. Macomber

    IPC分类号： G11C5/06 ,  H04L12/28 ,  H04L29/08

    CPC分类号： G11C5/066 ,  H04L12/28

    摘要： Serial high speed interconnect devices are integrated with semiconductor devices to reduce the number of input-output pins required for communications and control between a plurality of semiconductor devices. The serial high speed interconnect devices transfer the data serially at a rate fast enough to replace large parallel data and address buses that require one conductive path per bit of data. Eliminating large parallel data and address buses allows the integrated circuit assembly containing the semiconductor device to be smaller, simpler and lower in cost. The subsequent reduction in the size of the integrated circuits improves the layout density of electronic systems and reduces crosstalk and other undesirable signal transfer anomalies. The serial high speed interconnection devices are implemented with a low cost serial interface logic technology that may be easily implemented on a semiconductor die in conjunction with the main logic circuits.

    摘要翻译： 串行高速互连器件与半导体器件集成，以减少多个半导体器件之间的通信和控制所需的输入输出引脚的数量。 串行高速互连设备以足够快的速度串行传输数据，以便代替每一位数据需要一个导通路径的大型并行数据和地址总线。 消除大的并行数据和地址总线允许包含半导体器件的集成电路组件的成本更小，更简单和更低。 随后的集成电路尺寸的减小改善了电子系统的布局密度，并减少了串扰和其他不期望的信号传输异常。 串行高速互连设备采用低成本串行接口逻辑技术来实现，该技术可以与主逻辑电路一起在半导体管芯上容易地实现。

    Method and system for creating and validating low level structural description of electronic design from higher level, behavior-oriented description, including estimating power dissipation of physical implementation
    63.
    发明授权
    Method and system for creating and validating low level structural description of electronic design from higher level, behavior-oriented description, including estimating power dissipation of physical implementation 失效
    从较高级别创建和验证电子设计的低级结构描述的方法和系统，面向行为的描述，包括估计物理实现的功耗

    公开(公告)号：US5557531A

    公开(公告)日：1996-09-17

    申请号：US76738

    申请日：1993-06-14

    申请人： Michael D. Rostoker ,  Carlos Dangelo ,  Vijay Nagasamy

    发明人： Michael D. Rostoker ,  Carlos Dangelo ,  Vijay Nagasamy

    IPC分类号： G01R31/317 ,  G01R31/3183 ,  G06F11/26 ,  G06F17/50

    CPC分类号： G01R31/31704 ,  G01R31/318357 ,  G01R31/318364 ,  G01R31/318378 ,  G06F11/261 ,  G06F17/5022 ,  G06F17/5045

    摘要： A methodology for generating structural descriptions of complex digital devices from high-level descriptions and specifications is disclosed. The methodology uses a systematic technique to map and enforce consistency of the semantics imbedded in the intent of the original, high-level descriptions. The design activity is essentially a series of transformations operating upon various levels of design representations. At each level, the intended meaning (semantics) and formal software manipulations are captured to derive a more detailed level describing hardware meeting the design goals. Important features of the methodology are: capturing the users concepts, intent, specification, descriptions, constraints and trade-offs; architectural partitioning; what-if analysis at a high level; sizing estimation; timing estimation; architectural trade-off; conceptual design with implementation estimation; and timing closure. The methodology includes using estimators, based on data gathered over a number of realized designs, for partitioning and evaluating a design prior to logic synthesis. From the structural description, a physical implementation of the device is readily realized.Techniques are described for estimating the power and area requirements of the physical implementation of the device, at early, high level stages of the design process (e.g., at the system, behavioral, and register transfer level stages). The techniques are suited to the design of any semiconductor device, particularly CMOS devices.

    摘要翻译： 公开了一种用于从高级描述和规范生成复杂数字设备的结构描述的方法。 该方法使用系统的技术来绘制和实施嵌入原始高级描述意图的语义的一致性。 设计活动本质上是在各种级别的设计表示上运行的一系列变革。 在每个级别，捕获意图（语义）和正式的软件操作，以得到更详细的级别，描述符合设计目标的硬件。 方法的重要特征是：捕获用户的概念，意图，规范，描述，约束和权衡; 建筑分区; 高级别的假设分析; 尺寸估算; 定时估计; 建筑权衡; 概念设计与实施估计; 和时间关闭。 该方法包括使用估计器，基于在多个实现的设计上收集的数据，用于在逻辑综合之前对设计进行分区和评估。 从结构描述中，容易实现设备的物理实现。 描述了用于在设计过程的早期，高级阶段（例如，在系统，行为和寄存器传送级别阶段）处估计设备的物理实现的功率和面积要求的技术。 这些技术适用于任何半导体器件，特别是CMOS器件的设计。

    Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, including estimation and comparison of low-level design constraints
    64.
    发明授权
    Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, including estimation and comparison of low-level design constraints 失效
    从较高层次创建和验证电子设计的低级描述的方法和系统，面向行为的描述，包括低级设计约束的估计和比较

    公开(公告)号：US5544066A

    公开(公告)日：1996-08-06

    申请号：US76729

    申请日：1993-06-14

    申请人： Michael D. Rostoker ,  Carlos Dangelo ,  Vijay Nagasamy ,  Doron Mintz

    发明人： Michael D. Rostoker ,  Carlos Dangelo ,  Vijay Nagasamy ,  Doron Mintz

    IPC分类号： G01R31/317 ,  G01R31/3183 ,  G06F11/26 ,  G06F17/50

    CPC分类号： G01R31/31704 ,  G01R31/318357 ,  G01R31/318364 ,  G01R31/318378 ,  G06F11/261 ,  G06F17/5022 ,  G06F17/5045

    摘要： A methodology for generating structural descriptions of complex digital devices from high-level descriptions and specifications using a systematic technique to map and enforce consistency of the semantics imbedded in the intent of the original, high-level descriptions. The design activity is essentially a series of transformations operating upon various levels of design representations. At each level, the intended meaning (semantics) and formal software manipulations are captured to derive a more detailed level describing hardware meeting the design goals. Important features of the methodology are: capturing the users concepts, intent, specification, descriptions, constraints and trade-offs; architectural partitioning; what-if analysis at a high level; sizing estimation; timing estimation; architectural trade-off; conceptual design with implementation estimation; and timing closure. The methodology includes using estimators, based on data gathered over a number of realized designs, for partitioning and evaluating a design prior to logic synthesis. From the structural description, a physical implementation of the device is readily realized. Techniques are provided for constraint-driven partitioning of behavioral descriptions, and effective partitioning of high level descriptions for synthesis of multiple chips or blocks at the logic or register transfer levels. The partitioning technique is level-independent, and is integrated with the top-down design process, and takes into account constraints such as area, timing, power, package cost and testability. Iterative refinement is used to arrive at partitions that meet constraints imposed at high levels of abstraction.

    摘要翻译： 使用系统技术从高级描述和规范生成复杂数字设备的结构描述的方法，以映射和实施嵌入原始高级描述意图的语义的一致性。 设计活动本质上是在各种级别的设计表示上运行的一系列变革。 在每个级别，捕获意图（语义）和正式的软件操作，以得到更详细的级别，描述符合设计目标的硬件。 方法的重要特征是：捕获用户的概念，意图，规范，描述，约束和权衡; 建筑分区; 高级别的假设分析; 尺寸估算; 定时估计; 建筑权衡; 概念设计与实施估计; 和时间关闭。 该方法包括使用估计器，基于在多个实现的设计上收集的数据，用于在逻辑综合之前对设计进行分区和评估。 从结构描述中，容易实现设备的物理实现。 提供了用于行为描述的约束驱动分区的技术，以及用于在逻辑或寄存器传送级别合成多个芯片或块的高级描述的有效分区。 分区技术与层次无关，与自顶向下的设计流程相结合，并考虑到面积，时间，功耗，包装成本和可测试性等约束条件。 迭代细化用于达到满足在高抽象层次下施加的约束的分区。

    Testing and exercising individual, unsingulated dies on a wafer
    65.
    发明授权
    Testing and exercising individual, unsingulated dies on a wafer 失效
    在晶片上测试和运行单个，未加工的裸片

    公开(公告)号：US5442282A

    公开(公告)日：1995-08-15

    申请号：US908687

    申请日：1992-07-02

    申请人： Michael D. Rostoker ,  Carlos Dangelo ,  James Koford

    发明人： Michael D. Rostoker ,  Carlos Dangelo ,  James Koford

    IPC分类号： H01L21/66 ,  G01R31/28 ,  G01R31/3185 ,  G11C29/00 ,  H01L21/82

    CPC分类号： G01R31/2856 ,  G01R31/2884 ,  G01R31/2886 ,  G01R31/318505 ,  G01R31/318511 ,  G11C29/006 ,  G01R31/2831

    摘要： Signals (including probes) from an external system are selectively connected to a plurality of unsingulated dies on a semiconductor wafer with a minimum number of connections and an electronic selection mechanism resident on the wafer. The electronic selection mechanism is connected to the individual dies by conductive lines on the wafer. The electronic selection mechanism is capable of providing the external signals (or connecting the external probe) to a single die or groups of the dies, and electronically "walking through" the entire plurality of unsingulated dies. Redundant conductive lines may be provided. Diodes and/or fuses may be provided in conjunction with the conductive lines, to protect against various faults which may occur in the conductive lines. Redundant electronic selection mechanisms may also be provided to ensure the ability to selectively provide signals to the unsingulated dies.

    摘要翻译： 来自外部系统的信号（包括探针）选择性地连接到具有最少数量的连接的半导体晶片上的多个未折叠的管芯和驻留在晶片上的电子选择机构。 电子选择机构通过晶片上的导线连接到各个管芯。 电子选择机构能够将外部信号（或连接外部探针）提供给单个管芯或模具组，并以电子方式“走过”整个多个未接合的管芯。 可以提供冗余的导线。 二极管和/或保险丝可以与导电线一起提供，以防止可能在导电线路中发生的各种故障。 还可以提供冗余电子选择机构以确保选择性地向未压制模具提供信号的能力。

    Semiconductor package having programmable interconnect
    67.
    发明授权
    Semiconductor package having programmable interconnect 失效
    具有可编程互连的半导体封装

    公开(公告)号：US5264729A

    公开(公告)日：1993-11-23

    申请号：US921806

    申请日：1992-07-29

    申请人： Michael D. Rostoker ,  Yin Chang

    发明人： Michael D. Rostoker ,  Yin Chang

    IPC分类号： H01L23/498 ,  H01L23/525 ,  H01L23/538 ,  H01L27/118 ,  H01L23/48 ,  H01L29/40

    CPC分类号： H01L27/118 ,  H01L23/49827 ,  H01L23/525 ,  H01L23/5382 ,  H01L2924/0002 ,  H01L2924/15312

    摘要： A semiconductor package is described which has external connection points (pins, pads, etc.) which may be configured from outside of the package. In one embodiment, this is accomplished with programming holes which pass through and form contact surfaces with various conductors within the package. Conductive material is then deposited into selected holes, forming connections between all of the contact surfaces in any hole. In another embodiment, configurability is accomplished via conductive pads disposed on the exterior surface of the package. Conductive jumpers are then used to connect selected pads. An auxiliary externally effected power plane and bus-bar structure are also described.

    摘要翻译： 描述了具有可以从封装外部配置的外部连接点（引脚，焊盘等）的半导体封装。 在一个实施例中，这是通过编程孔完成的，该孔通过并与封装内的各种导体形成接触表面。 然后将导电材料沉积到选定的孔中，在任何孔中的所有接触表面之间形成连接。 在另一个实施例中，可配置性通过设置在包装的外表面上的导电垫完成。 然后使用导电跳线连接所选择的焊盘。 还描述了辅助外部实现的电源平面和汇流条结构。

    METHOD AND SYSTEM FOR CREATING, DERIVING AND VALIDATING STRUCTURAL DESCRIPTION OF ELECTRONIC SYSTEM FROM HIGHER LEVEL, BEHAVIOR-ORIENTED DESCRIPTION, INCLUDING INTERACTIVE SCHEMATIC DESIGN AND SIMULATION
    69.
    发明授权
    METHOD AND SYSTEM FOR CREATING, DERIVING AND VALIDATING STRUCTURAL DESCRIPTION OF ELECTRONIC SYSTEM FROM HIGHER LEVEL, BEHAVIOR-ORIENTED DESCRIPTION, INCLUDING INTERACTIVE SCHEMATIC DESIGN AND SIMULATION 失效
    用于从高级创建，导出和确认电子系统的结构描述的方法和系统，基于行为的描述，包括交互式设计和模拟

    公开(公告)号：US06470482B1

    公开(公告)日：2002-10-22

    申请号：US08689204

    申请日：1996-08-05

    申请人： Michael D. Rostoker ,  Carlos Dangelo ,  Daniel R. Watkins

    发明人： Michael D. Rostoker ,  Carlos Dangelo ,  Daniel R. Watkins

    IPC分类号： G06F1750

    CPC分类号： G01R31/318357 ,  G01R31/31704 ,  G01R31/318364 ,  G01R31/318378 ,  G06F11/261 ,  G06F17/5022 ,  G06F17/5045

    摘要： A system for interactive design, synthesis and simulation of an electronic system allowing a user to design a system either by specification of a behavioral model in a high level language such as VHDL or by graphical entry. The user can view full or partial simulation and design results simultaneously, on a single display window. The synthesis process uses a systematic technique to map and enforce consistency of the semantics imbedded in the intent of the original, high-level descriptions. The design activity is generally a series of transformations operating upon various levels of design representations. At each level, the design can be simulated and reviewed in schematic diagram form. The simulation results can be displayed immediately adjacent to signal lines on the diagram to which they correspond. In one embodiment, design rule violations are processed by an expert system to suggest possible corrections or alterations to the design which will eliminate the design rule violations. Schematic diagram and simulation displays showing those portions of the electronic system and simulated signal patterns which are related to the design rule violations are used to help the user identify and appropriately correct problems in the design.

    摘要翻译： 一种用于电子系统的交互式设计，综合和仿真的系统，允许用户通过以诸如VHDL或图形输入的高级语言的行为模型的规范来设计系统。 用户可以在单个显示窗口上同时查看完整或部分模拟和设计结果。 综合过程使用系统的技术来绘制和强化嵌入原始高级描述意图的语义的一致性。 设计活动通常是在各种级别的设计表示上进行的一系列转换。 在每个层次上，可以以原理图形式对设计进行模拟和审查。 模拟结果可以与它们对应的图上的信号线紧邻显示。 在一个实施例中，设计规则违规由专家系统处理，以建议可能的更正或改变设计，这将消除设计规则违规。 示意图和模拟显示显示了与设计规则违规相关的电子系统部分和模拟信号模式的部分，用于帮助用户识别和适当地纠正设计中的问题。

    FPGA with embedded content-addressable memory
    70.
    发明授权
    FPGA with embedded content-addressable memory 失效
    FPGA具有嵌入式内容可寻址存储器

    公开(公告)号：US6147890A

    公开(公告)日：2000-11-14

    申请号：US166503

    申请日：1998-10-05

    申请人： Keiichi Kawana ,  Michael D. Rostoker

    发明人： Keiichi Kawana ,  Michael D. Rostoker

    IPC分类号： G11C15/00 ,  H03K19/177

    CPC分类号： H03K19/1776 ,  G11C15/00

    摘要： Content Addressable Memory (CAM) core is integrated and interfaced with a configurable logic core (e.g., FPGA) on a single integrated circuit (IC) chip to permit a user to change algorithms for and to tailor word length to a particular application. Significant improvements in fetch times and overhead are achieved. An electronic component (e.g., integrated circuit) incorporating the technique is suitably included in a system or subsystem having electrical functionality, such as general purpose computers, telecommunications devices, and the like.

    摘要翻译： 内容可寻址存储器（CAM）核心集成在单个集成电路（IC）芯片上与可配置的逻辑核心（例如FPGA）接口，以允许用户改变用于特定应用的字长的算法和定制字长度。 实现了提取时间和开销的显着改进。 结合该技术的电子部件（例如，集成电路）适当地包括在具有电功能的系统或子系统中，例如通用计算机，电信设备等。