-
公开(公告)号：US20160111167A1
公开(公告)日：2016-04-21
申请号：US14518727
申请日：2014-10-20
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Feng Pan , Ramin Ghodsi , Qiang Tang
IPC: G11C16/26
CPC classification number: G11C16/3427 , G11C16/0483 , G11C16/08 , G11C16/16 , G11C16/24 , G11C16/26
Abstract: Apparatuses and methods for reducing read disturb are described herein. An example apparatus may include a first memory subblock including a first select gate drain (SGD) switch and a first select gate source (SGS) switch, a second memory subblock including a second SGD switch and a second SGS switch, and an access line associated with the first and second memory subblocks. The apparatus may include a control unit configured to enable the first and second SGD switches and the first and second SGS switches during a first portion of a read operation and to provide a first voltage on the access line during the first portion. The control unit may be configured to disable the first SGD switch and the first SGS switches during a second portion of the read operation and to provide a second voltage on the access line during the second portion.
Abstract translation: 本文描述了用于减少读取干扰的装置和方法。 示例性装置可以包括包括第一选择栅极漏极（SGD）开关和第一选择栅极源（SGS）开关的第一存储器子块，包括第二SGD开关和第二SGS开关的第二存储器子块以及与之相关联的存取线 与第一和第二存储器子块。 该装置可以包括控制单元，其被配置为在读取操作的第一部分期间使第一和第二SGD开关以及第一和第二SGS开关能够实现，并且在第一部分期间在存取线上提供第一电压。 控制单元可以被配置为在读取操作的第二部分期间禁用第一SGD开关和第一SGS开关，并且在第二部分期间在接入线上提供第二电压。
-
公开(公告)号：US20160027793A1
公开(公告)日：2016-01-28
申请号：US14877997
申请日：2015-10-08
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Aaron Yip , Qiang Tang , Chang Wan Ha
IPC: H01L27/115 , G11C16/06
CPC classification number: H01L27/11556 , G11C16/06 , H01L27/115 , H01L27/11565 , H01L27/1157 , H01L27/11575 , H01L27/11582
Abstract: Semiconductor devices, such as three-dimensional memory devices, include a memory array including a stack of conductive tiers and a stair step structure. The stair step structure is positioned between first and second portions of the memory array and includes contact regions for respective conductive tiers of the stack of conductive tiers. The first portion of the memory array includes a first plurality of select gates extending in a particular direction over the stack. The second portion of the memory array includes a second plurality of select gates also extending in the particular direction over the stack of conductive tiers. Methods of forming and methods of operating such semiconductor devices, including vertical memory devices, are also disclosed.
-
公开(公告)号：US20130215681A1
公开(公告)日：2013-08-22
申请号：US13849937
申请日：2013-03-25
Applicant: Micron Technology, Inc.
Inventor： Qiang Tang
IPC: G11C16/28
CPC classification number: G11C16/28 , G11C16/0483
Abstract: Sense amplifiers and memory devices include a current source coupled to a bit line connection, a sensing transistor having a control gate coupled to the bit line connection, and a data latch coupled to a source/drain region of the sensing transistor. The sensing transistor has a channel length greater than one and a half times the channel length of a conventional transistor of a semiconductor manufacturing process utilized to form the sense amplifier and/or the current source comprises a transistor having a channel length greater than one and a half times the channel length of a conventional transistor of the semiconductor manufacturing process utilized to form the sense amplifier
Abstract translation: 感测放大器和存储器件包括耦合到位线连接的电流源，具有耦合到位线连接的控制栅极的感测晶体管，以及耦合到感测晶体管的源极/漏极区域的数据锁存器。 感测晶体管具有大于用于形成读出放大器和/或电流源的半导体制造工艺的常规晶体管的沟道长度的一倍半的沟道长度，包括沟道长度大于1的晶体管和 用于形成读出放大器的半导体制造工艺的常规晶体管的沟道长度的一半
-
公开(公告)号：US11749349B2
公开(公告)日：2023-09-05
申请号：US17873216
申请日：2022-07-26
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Qiang Tang , Ramin Ghodsi
CPC classification number: G11C16/10 , G11C7/1057 , G11C7/1084 , G11C16/0483 , G11C16/26 , G11C29/022 , G11C29/028 , G11C29/50008 , H03K19/0005 , H03K19/018528 , G11C2207/2254
Abstract: Memory including an array of memory cells might include an input buffer having calibration circuitry, a first input, a second input, and an output; and calibration logic having an input selectively connected to the output of the input buffer and comprising an output connected to the calibration circuitry, wherein the calibration logic is configured to cause the memory to determine whether the input buffer exhibits offset while a particular voltage level is applied to the first and second inputs of the input buffer, and, in response to determining that the selected input buffer exhibits offset, apply an adjustment to the calibration circuitry while the particular voltage level is applied to the first and second inputs until a logic level of the output of the selected input buffer transitions.
-
公开(公告)号：US10854295B2
公开(公告)日：2020-12-01
申请号：US16178989
申请日：2018-11-02
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Qiang Tang , Ramin Ghodsi
Abstract: Methods of operating an integrated circuit device, and integrated circuit devices configured to perform methods, including applying a particular voltage level to a first input of an input/output (I/O) buffer and to a second input of the I/O buffer, determining whether the I/O buffer is deemed to exhibit offset, and applying an adjustment to the I/O buffer offset while applying the particular voltage level to the first input of the I/O buffer and to the second input of the I/O buffer if the I/O buffer is deemed to exhibit offset.
-
Patent Agency Ranking
公开(公告)号：US10541032B2
公开(公告)日：2020-01-21
申请号：US15591700
申请日：2017-05-10
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Qiang Tang , Theodore T. Pekny
Abstract: Methods of operating apparatus include receiving user data for programming to a grouping of memory cells of the apparatus, associating an address of the grouping of memory cells with the user data, determining whether power loss to the apparatus is indicated while programming the user data to the grouping of memory cells, and if power loss to the apparatus is indicated while programming the user data to the grouping of memory cells, programming the address of the grouping of memory cells to a different grouping of memory cells of the apparatus. Methods of operating apparatus further include checking whether power loss to the apparatus during programming of user data to a grouping of memory cells of the apparatus is indicated, and, when power loss is indicated, checking feature settings of the apparatus to determine a location of the apparatus containing an address of the grouping of memory cells, and recovering the address of the grouping of memory cells from the determined location.
-
公开(公告)号：US10515692B2
公开(公告)日：2019-12-24
申请号：US16023042
申请日：2018-06-29
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Qiang Tang , Xiaojiang Guo , Ramin Ghodsi
Abstract: Methods of operating a memory device applying a programming pulse having a plurality of different voltage levels to an access line coupled to a plurality of memory cells, enabling a particular memory cell of the plurality of memory cells for programming while the programming pulse has a particular voltage level of the plurality of different voltage levels, and, after enabling the particular memory cell for programming, inhibiting the particular memory cell from programming while the programming pulse has a second voltage level of the plurality of different voltage levels, different than the particular voltage level.
-
公开(公告)号：US20190288598A1
公开(公告)日：2019-09-19
申请号：US16430761
申请日：2019-06-04
Applicant: Micron Technology, Inc.
Inventor： Michele Piccardi , Xiaojiang Guo , Qiang Tang
IPC: H02M3/07
Abstract: An electronic device includes a reconfigurable charge pump including pump units that can be arranged differently for varying an output voltage generated by the reconfigurable charge pump; a pump regulator coupled to the reconfigurable charge pump, the pump regulator configured to monitor the output voltage and turn the reconfigurable charge pump on or off based on the output voltage; and an arrangement control mechanism coupled to the pump regulator, the arrangement control mechanism configured to control operation of the pump regulator based on the output voltage to generate arrangement control output, wherein the arrangement control output controls electrical connections between the pump units.
-
公开(公告)号：US20190068052A1
公开(公告)日：2019-02-28
申请号：US16009128
申请日：2018-06-14
Applicant: Micron Technology, Inc.
Inventor： Michele Piccardi , Xiaojiang Guo , Qiang Tang
IPC: H02M3/07
CPC classification number: H02M3/07
Abstract: An electronic device includes a reconfigurable charge pump including pump units that can be arranged differently for varying an output voltage generated by the reconfigurable charge pump; a pump regulator coupled to the reconfigurable charge pump, the pump regulator configured to monitor the output voltage and turn the reconfigurable charge pump on or off based on the output voltage; and an arrangement control mechanism coupled to the pump regulator, the arrangement control mechanism configured to control operation of the pump regulator based on the output voltage to generate arrangement control output, wherein the arrangement control output controls electrical connections between the pump units.
-
公开(公告)号：US20190066796A1
公开(公告)日：2019-02-28
申请号：US15693133
申请日：2017-08-31
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Xiaojiang Guo , Guanglei An , Qiang Tang
CPC classification number: G11C16/12 , G11C8/08 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/3459
Abstract: Methods of operating a memory include determining a target voltage level for an access line voltage, determining a target overdrive voltage level for gating the access line voltage to an access line coupled to a plurality of memory cells, generating a voltage level for the access line voltage in response to its target voltage level and generating a voltage level for gating the access line voltage to the access line in response to the target overdrive voltage level, and applying the access line voltage to the access line while applying the voltage level for gating the access line voltage to a control gate of a string driver connected to the access line. Apparatus include a voltage regulator having variable resistance paths between a voltage signal node and an output node, and between the voltage signal node and an input of a comparator of the voltage regulator.
-
-
-
-
-
-
-
-
-
Search Results
103
records
(took 0.021 seconds)
