公开(公告)号：US6159782A

公开(公告)日：2000-12-12

申请号：US369217

申请日：1999-08-05

Applicant: Qi Xiang ,  Ming-Ren Lin

Inventor： Qi Xiang ,  Ming-Ren Lin

IPC: H01L21/336 ,  H01L21/8238 ,  H01L21/8234

CPC classification number: H01L21/823857 ,  H01L29/66545

Abstract: A method for fabricating short channel field effect transistors with dual gates and with a gate dielectric having a high dielectric constant. The field effect transistor is initially fabricated to have a sacrificial gate dielectric and a dummy gate electrode. Any fabrication process, such as an activation anneal or a salicidation anneal of the source and drain of the field effect transistor, using relatively high temperature is performed with the field effect transistor having the sacrificial gate dielectric and the dummy gate electrode. The dummy gate electrode and the sacrificial gate dielectric are etched from the field effect transistor to form a gate opening. A layer of dielectric with high dielectric constant is deposited on the side wall and the bottom wall of the gate opening, and amorphous gate electrode material, such as amorphous silicon, is deposited to fill the gate opening after the layer of dielectric has been deposited. Dual gates for both an N-channel field effect transistor and a P-channel field effect transistor are formed by doping the amorphous gate electrode material with an N-type dopant for an N-channel field effect transistor, and by doping the amorphous gate electrode material with a P-type dopant for a P-channel field effect transistor. The amorphous gate electrode material in the gate opening is then annealed at a relatively low temperature, such as 600.degree. Celsius, using a solid phase crystallization process to convert the amorphous gate electrode material, such as amorphous silicon, into polycrystalline gate electrode material, such as polycrystalline silicon. Thus, relatively low temperatures are used in the present invention to preserve the integrity of the gate dielectric having the high dielectric constant.

Abstract translation: 一种用于制造具有双栅极和具有高介电常数的栅极电介质的短沟道场效应晶体管的方法。 场效应晶体管最初被制造成具有牺牲栅极电介质和虚拟栅电极。 使用具有牺牲栅极电介质和虚拟栅电极的场效应晶体管，使用相对较高的温度进行任何制造工艺，例如场效应晶体管的源极和漏极的激活退火或腐蚀退火。 从场效应晶体管蚀刻伪栅电极和牺牲栅电介质以形成栅极开口。 在栅极的侧壁和底壁上沉积具有高介电常数的电介质层，并沉积诸如非晶硅之类的非晶态栅电极材料，以在沉积介电层之后填充栅极开口。 通过用N型掺杂剂掺杂非晶栅电极材料来形成用于N沟道场效应晶体管和P沟道场效应晶体管的双栅极，并且通过掺杂非晶栅电极 具有用于P沟道场效应晶体管的P型掺杂剂的材料。 然后，使用固相结晶工艺，在诸如600℃的较低温度下将栅极开口中的非晶栅电极材料退火，将非晶态的非晶硅等非晶态栅电极材料转换为多晶栅电极材料， 作为多晶硅。 因此，在本发明中使用相对较低的温度来保持具有高介电常数的栅极电介质的完整性。

公开(公告)号：US6083798A

公开(公告)日：2000-07-04

申请号：US84322

申请日：1998-05-26

Applicant: Ming-Ren Lin

Inventor： Ming-Ren Lin

IPC: H01L21/225 ,  H01L21/336 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L29/66492 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/7833 ,  H01L21/2257

Abstract: A semiconductor device and a method of making the device with a raised source/drain has a semiconductive material that is non-selectively deposited in a layer over the device area. The semiconductive material is then etched to form spacers that will form the raised soure/drain areas following doping of the spacers. The gate of the semiconductor device is protected during the etching by an etch stop layer that is grown or deposited over the structure to be protected, e.g., the gate, prior to the deposition of the semiconductive material layer. Lightly doped drain ion implantation is performed prior to the formation of the spacers, and source-drain ion implantation is performed preferably after the formation of the spacers, to create the shallow junctions.

Abstract translation: 半导体器件和使具有升高的源极/漏极的器件的方法具有非选择性地沉积在器件区域上的层中的半导体材料。 然后蚀刻半导体材料以形成在掺杂间隔物之后将形成升高的固体/漏极区的间隔物。 半导体器件的栅极在蚀刻期间被保护，该蚀刻停止层在沉积半导体材料层之前生长或沉积在要保护的结构（例如栅极）上。 在形成间隔物之前进行轻掺杂的漏极离子注入，优选在形成间隔物之后进行源极 - 漏极离子注入，以产生浅结。

公开(公告)号：US5904528A

公开(公告)日：1999-05-18

申请号：US785213

申请日：1997-01-17

Applicant: Ming-Ren Lin ,  Peng Fang ,  Donald L. Wollesen

Inventor： Ming-Ren Lin ,  Peng Fang ,  Donald L. Wollesen

IPC: H01L21/266 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L29/66659 ,  H01L21/266 ,  H01L21/823814 ,  H01L29/7835

Abstract: Asymmetrically doped source/drain regions of a transistor are formed employing protective insulating layers to prevent a portion of the gate electrode from receiving an excessive impurity implantation dose and penetrating through the underlying gate insulating layer into the semiconductor substrate. Sidewall spacers are employed during heavy implantation.

公开(公告)号：US06958264B1

公开(公告)日：2005-10-25

申请号：US09824933

申请日：2001-04-03

Applicant: Ming-Ren Lin

Inventor： Ming-Ren Lin

IPC: H01L21/322 ,  H01L21/335 ,  H01L21/8232

CPC classification number: H01L21/3221

Abstract: A method of manufacturing a semiconductor device on a silicon-on-insulator wafer including a silicon active layer having at least two die pads formed thereon, the at least two die pads separated by at least one scribe lane, including the steps of forming at least one cavity through the silicon active layer in the at least one scribe lane; forming at least one gettering plug in each said cavity, each said gettering plug comprising doped fill material containing a plurality of gettering sites; and subjecting the wafer to conditions to getter at least one impurity into the plurality of gettering sites. A silicon-on-insulator semiconductor wafer including a silicon active layer; a plurality of die pads formed in the silicon active layer; at least one scribe lane between and separating adjacent die pads; and at least one gettering plug in the at least one scribe lane, wherein the at least one gettering plug extends through the silicon active layer and the gettering plug comprises a doped fill material having a plurality of gettering sites.

Abstract translation: 一种在绝缘体上硅晶片上制造半导体器件的方法，其包括其上形成有至少两个管芯焊盘的硅有源层，所述至少两个管芯焊盘由至少一个划线通道隔开，包括至少形成 通过所述至少一个划线中的所述硅有源层的一个空腔; 在每个所述空腔中形成至少一个吸气塞，每个所述吸气塞包括含有多个吸气位点的掺杂填料; 并且使所述晶片经受条件以将至少一种杂质吸入所述多个吸气部位。 包括硅有源层的绝缘体上硅半导体晶片; 形成在所述硅有源层中的多个管芯焊盘; 在相邻的管芯焊盘之间和分离相邻的管芯焊盘之间的至少一个划线; 以及在所述至少一个划线中的至少一个吸气塞，其中所述至少一个吸气塞延伸穿过所述硅有源层，并且所述吸气塞包括具有多个吸气位点的掺杂填料。

公开(公告)号：US06790782B1

公开(公告)日：2004-09-14

申请号：US10157450

申请日：2002-05-29

Applicant: Chih-Yuh Yang ,  Cyrus E. Tabery ,  Ming-Ren Lin

Inventor： Chih-Yuh Yang ,  Cyrus E. Tabery ,  Ming-Ren Lin

IPC: H01L21302

CPC classification number: H01L21/28123 ,  H01L21/0337 ,  H01L21/28273 ,  H01L29/517

Abstract: The invention provides a method of small geometry gate formation on the surface of a high-K gate dielectric. The method provides for processing steps that include gate pattern trimming, gate stack etch, and removal of exposed regions of the high-K dielectric to be performed efficiently in a single etch chamber. As such, process complexity and processing costs are reduced while throughput and overall process efficiency is improved. The method includes fabricating a high-K gate dielectric etch stop dielectric layer on the surface of a silicon substrate to protect the silicon substrate from erosion during an etch step and to prove a gate dielectric. A polysilicon layer is fabricated above the high-K dielectric layer. An anti-reflective coating layer above the polysilicon layer, and a mask is fabricated above the anti-reflective coating layer to define a gate region and an erosion region. The sequence of etching steps discussed above are performed in-situ in an enclosed high density plasma etching chamber environment.

Abstract translation: 本发明提供了在高K栅极电介质的表面上形成小几何形状的栅极的方法。 该方法提供了处理步骤，其包括在单个蚀刻室中有效执行的栅极图案修整，栅极堆叠蚀刻和去除高K电介质的暴露区域。 因此，降低了处理复杂性和处理成本，同时提高了吞吐量和整体处理效率。 该方法包括在硅衬底的表面上制造高K栅电介质蚀刻阻挡介电层，以在蚀刻步骤期间保护硅衬底免受腐蚀并证明栅极电介质。 在高K电介质层上方制造多晶硅层。 在多晶硅层上方的抗反射涂层和在抗反射涂层上方制造掩模以限定栅极区域和侵蚀区域。 上述蚀刻步骤的顺序在封闭的高密度等离子体蚀刻室环境中原位进行。

公开(公告)号：US06787864B2

公开(公告)日：2004-09-07

申请号：US10335492

申请日：2002-12-31

Applicant: Eric N. Paton ,  Qi Xiang ,  Paul R. Besser ,  Ming-Ren Lin ,  Minh V. Ngo ,  Haihong Wang

Inventor： Eric N. Paton ,  Qi Xiang ,  Paul R. Besser ,  Ming-Ren Lin ,  Minh V. Ngo ,  Haihong Wang

IPC: H01L2972

CPC classification number: H01L29/4933 ,  H01L21/28052 ,  H01L29/1054 ,  H01L29/4908 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66795 ,  H01L2029/7858

Abstract: A MOSFET gate or a MOSFET source or drain region comprises silicon germanium or polycrystalline silicon germanium. Silicidation with nickel is performed to form a nickel germanosilicide that preferably comprises the monosilicide phase of nickel silicide. The inclusion of germanium in the silicide provides a wider temperature range within which the monosilicide phase may be formed, while essentially preserving the superior sheet resistance exhibited by nickel monosilicide. As a result, the nickel germanosilicide is capable of withstanding greater temperatures during subsequent processing than nickel monosilicide, yet provides approximately the same sheet resistance and other beneficial properties as nickel monosilicide.

公开(公告)号：US06437404B1

公开(公告)日：2002-08-20

申请号：US09636239

申请日：2000-08-10

Applicant: Qi Xiang ,  Wei Long ,  Ming-Ren Lin

Inventor： Qi Xiang ,  Wei Long ,  Ming-Ren Lin

IPC: H01L2701

CPC classification number: H01L29/78696 ,  H01L21/26533 ,  H01L21/28079 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/78603

Abstract: A fully-depleted semiconductor-on-insulator (SOI) transistor device has an SOI substrate with a buried insulator layer having a nonuniform depth relative to a top surface of the substrate, the buried insulator layer having a shallow portion closer to the top surface than deep portions of the layer. A gate is formed on a thin semiconductor layer between the top surface and the shallow portion of the insulator layer. Source and drain regions are formed on either side of the gate, the source and drain regions each being atop one of the deep portions of the buried insulator layer. The source and drain regions thereby have a greater thickness than the thin semiconductor layer. Thick silicide regions formed in the source and drain regions have low parasitic resistance. A method of making the transistor device includes forming a dummy gate structure on an SOI substrate, and using the dummy gate structure to control the depth of an implantation to form the nonuniform depth buried insulator layer.

Abstract translation: 完全耗尽的绝缘体上半导体（SOI）晶体管器件具有SOI衬底，其具有相对于衬底的顶表面具有不均匀深度的掩埋绝缘体层，所述掩埋绝缘体层具有靠近顶表面的较浅部分比 层的深部分。 栅极形成在绝缘体层的顶表面和浅部之间的薄半导体层上。 源极和漏极区域形成在栅极的任一侧上，源极和漏极区域分别位于掩埋绝缘体层的深部之一的顶部。 源极和漏极区域因此具有比薄的半导体层更大的厚度。 形成在源区和漏区的厚硅化物区具有低寄生电阻。 制造晶体管器件的方法包括在SOI衬底上形成虚拟栅极结构，并且使用虚拟栅极结构来控制注入的深度以形成不均匀深度的掩埋绝缘体层。

公开(公告)号：US06369429B1

公开(公告)日：2002-04-09

申请号：US09641727

申请日：2000-08-21

Applicant: Shekhar Pramanick ,  Ming-Ren Lin ,  Qi Xiang

Inventor： Shekhar Pramanick ,  Ming-Ren Lin ,  Qi Xiang

IPC: H01L2352

CPC classification number: H01L21/28518 ,  H01L21/28568

Abstract: Low resistance contacts are formed on source/drain regions and gate electrodes by selectively depositing a reaction barrier layer and selectively depositing a metal layer on the reaction barrier layer. Embodiments include selectively depositing an alloy of cobalt and tungsten which functions as a reaction barrier layer preventing silicidation of a layer of nickel or cobalt selectively deposited thereon. Embodiments also include tailoring the composition of the cobalt tungsten alloy so that a thin silicide layer is formed thereunder for reduced contact resistance.

Abstract translation: 通过选择性地沉积反应阻挡层并在反应阻挡层上选择性地沉积金属层，在源/漏区和栅电极上形成低电阻触点。 实施方案包括选择性沉积钴和钨的合金，其用作反应阻挡层，防止选择性沉积在其上的镍或钴层的硅化。 实施例还包括定制钴钨合金的组成，使得在其下形成薄的硅化物层以降低接触电阻。

公开(公告)号：US06271132B1

公开(公告)日：2001-08-07

申请号：US09303693

申请日：1999-05-03

Applicant: Qi Xiang ,  Matthew S. Buynoski ,  Ming-Ren Lin

Inventor： Qi Xiang ,  Matthew S. Buynoski ,  Ming-Ren Lin

IPC: H01L2144

CPC classification number: H01L29/6659 ,  H01L21/823814 ,  H01L21/823857 ,  H01L29/456 ,  H01L29/66545 ,  H01L29/7833

Abstract: A method of fabricating a transistor having shallow source and drain extensions utilizes a self-aligned contact. The drain extensions are provided through an opening between a contact area and the gate structure. A high-k gate dielectric material can be utilized. P-MOS and N-MOS transistors can be created according to the disclosed method.

Abstract translation: 制造具有浅源极和漏极延伸的晶体管的方法利用自对准接触。 漏极延伸部分通过接触区域和栅极结构之间的开口提供。 可以使用高k栅介电材料。 可以根据所公开的方法创建P-MOS和N-MOS晶体管。

公开(公告)号：US06238960B1

公开(公告)日：2001-05-29

申请号：US09483400

申请日：2000-01-14

Applicant: Witold P. Maszara ,  Srinath Krishnan ,  Ming-Ren Lin

Inventor： Witold P. Maszara ,  Srinath Krishnan ,  Ming-Ren Lin

IPC: H01L21336

CPC classification number: H01L29/66772 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/78612 ,  H01L29/78621 ,  H01L29/78654

Abstract: A method (100) of forming a transistor (50, 80) includes forming a gate oxide (120) over a portion of a semiconductor material (56, 122) and forming a doped polysilicon film (124) having a dopant concentration over the gate oxide (122). Subsequently, the doped polysilicon film (124) is etched to form a gate electrode (52) overlying a channel region (58) in the semiconductor material (56, 122), wherein the gate electrode (52) separates the semiconductor material into a first region (60) and a second region (68) having the channel region (58) therebetween. The method (100) further includes forming a drain extension region (64) in the first region (60) and a source extension region (72) in the second region (68), and forming a drain region (62) in the first region (60) and a source region (70) in the second region (68). The source/drain formation is such that the drain and source regions (62, 70) have a dopant concentration which is less than the polysilicon film (124) doping concentration. The lower doping concentration in the source/drain regions (62, 70) lowers the junction capacitance and provides improved control of floating body effects when employed in SOI type processes.

Abstract translation: 形成晶体管（50,80）的方法（100）包括在半导体材料（56,122）的一部分上形成栅极氧化物（120），并形成掺杂浓度超过栅极的掺杂多晶硅膜（124） 氧化物（122）。 随后，蚀刻掺杂多晶硅膜（124）以形成覆盖半导体材料（56,122）中的沟道区域（58）的栅电极（52），其中栅电极（52）将半导体材料分离成第一 区域（60）和在其间具有沟道区（58）的第二区域（68）。 方法（100）还包括在第一区域（60）中形成漏极延伸区域（64）和在第二区域（68）中形成源极延伸区域（72），并且在第一区域 （60）和第二区域（68）中的源极区域（70）。 源极/漏极形成使得漏极和源极区域（62,70）具有小于多晶硅膜（124）掺杂浓度的掺杂剂浓度。 源极/漏极区域（62,70）中的较低掺杂浓度降低了结电容，并且当用于SOI类型工艺时，提供对浮体效应的改进的控制。