公开(公告)号：US20090142921A1

公开(公告)日：2009-06-04

申请号：US12363588

申请日：2009-01-30

申请人： Christopher J. Petti

发明人： Christopher J. Petti

IPC分类号： H01L21/4763 ,  H01L21/768 ,  H01L21/465 ,  H01L21/463

CPC分类号： H01L21/768 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76829 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a first preferred embodiment of the present invention, conductive features are formed on a first dielectric etch stop layer, and a second dielectric material is deposited over and between the conductive features. A via etch to the conductive features which is selective between the first and second dielectrics will stop on the dielectric etch stop layer, limiting overetch. In a second embodiment, a plurality of conductive features is formed in a subtractive pattern and etch process, filled with a dielectric fill, and then a surface formed coexposing the conductive features and dielectric fill. A dielectric etch stop layer is deposited on the surface, then a third dielectric covers the dielectric etch stop layer. When a contact is etched through the third dielectric, this selective etch stops on the dielectric etch stop layer. A second etch makes contact to the conductive features.

摘要翻译： 在本发明的第一优选实施例中，导电特征形成在第一电介质蚀刻停止层上，并且第二电介质材料沉积在导电特征之上和之间。 在第一和第二电介质之间选择性的导电特征的通孔蚀刻将停止在电介质蚀刻停止层上，限制过蚀刻。 在第二实施例中，多个导电特征以消减图案和蚀刻工艺形成，填充有电介质填充物，然后形成为与导电特征和电介质填充物共同构成的表面。 电介质蚀刻停止层沉积在表面上，然后第三电介质覆盖电介质蚀刻停止层。 当通过第三电介质蚀刻接触时，该选择性蚀刻停止在电介质蚀刻停止层上。 第二蚀刻与导电特征接触。

公开(公告)号：US07499304B2

公开(公告)日：2009-03-03

申请号：US11461419

申请日：2006-07-31

申请人： Roy E. Scheuerlein ,  Christopher J. Petti

发明人： Roy E. Scheuerlein ,  Christopher J. Petti

IPC分类号： G11C11/00

CPC分类号： G11C17/16 ,  G11C17/165

摘要： A one-time field programmable (OTP) memory cell with related manufacturing and programming techniques is disclosed. An OTP memory cell in accordance with one embodiment includes at least one resistance change element in series with a steering element. The memory cell is field programmed using a reverse bias operation that can reduce leakage currents through the array as well as decrease voltage levels that driver circuitry must normally produce in program operations. An array of memory cells can be fabricated by switching the memory cells from their initial virgin state to a second resistance state during the manufacturing process. In one embodiment, the factory switching operation can include popping an anti-fuse of each memory cell to set them into the second resistance state. The array of memory cells in the second resistance state are provided to an end-user. Control circuitry is also provided with the memory array that can switch the resistance of selected cells back toward their initial resistance state to program the array in accordance with data received from a user or host device.

摘要翻译： 公开了具有相关制造和编程技术的一次性现场可编程（OTP）存储单元。 根据一个实施例的OTP存储器单元包括与转向元件串联的至少一个电阻变化元件。 使用反向偏置操作来对存储单元进行现场编程，该反向偏压操作可以减少通过阵列的漏电流，以及降低驱动电路在程序运行中通常产生的电压电平。 可以通过在制造过程中将存储器单元从其初始状态切换到第二电阻状态来制造存储器单元阵列。 在一个实施例中，出厂切换操作可以包括弹出每个存储单元的反熔丝以使它们成为第二电阻状态。 将第二电阻状态的存储单元的阵列提供给终端用户。 控制电路还具有存储器阵列，其可以将所选择的单元的电阻切换回其初始电阻状态，以根据从用户或主机设备接收的数据对阵列进行编程。

公开(公告)号：US20090001347A1

公开(公告)日：2009-01-01

申请号：US11819989

申请日：2007-06-29

申请人： Tanmay Kumar ,  Christopher J. Petti

发明人： Tanmay Kumar ,  Christopher J. Petti

IPC分类号： H01L45/00

CPC分类号： H01L27/24 ,  G11C13/0004

摘要： A nonvolatile memory device includes a semiconductor diode steering element, and a semiconductor read/write switching element.

摘要翻译： 非易失性存储器件包括半导体二极管操作元件和半导体读/写开关元件。

公开(公告)号：US20080025067A1

公开(公告)日：2008-01-31

申请号：US11461419

申请日：2006-07-31

申请人： Roy E. Scheuerlein ,  Christopher J. Petti

发明人： Roy E. Scheuerlein ,  Christopher J. Petti

IPC分类号： G11C11/00

CPC分类号： G11C17/16 ,  G11C17/165

摘要： A one-time field programmable (OTP) memory cell with related manufacturing and programming techniques is disclosed. An OTP memory cell in accordance with one embodiment includes at least one resistance change element in series with a steering element. The memory cell is field programmed using a reverse bias operation that can reduce leakage currents through the array as well as decrease voltage levels that driver circuitry must normally produce in program operations. An array of memory cells can be fabricated by switching the memory cells from their initial virgin state to a second resistance state during the manufacturing process. In one embodiment, the factory switching operation can include popping an anti-fuse of each memory cell to set them into the second resistance state. The array of memory cells in the second resistance state are provided to an end-user. Control circuitry is also provided with the memory array that can switch the resistance of selected cells back toward their initial resistance state to program the array in accordance with data received from a user or host device.

摘要翻译： 公开了具有相关制造和编程技术的一次性现场可编程（OTP）存储单元。 根据一个实施例的OTP存储器单元包括与转向元件串联的至少一个电阻变化元件。 使用反向偏置操作来对存储单元进行现场编程，该反向偏压操作可以减少通过阵列的漏电流，以及降低驱动器电路在程序运行中通常产生的电压电平。 可以通过在制造过程中将存储器单元从其初始状态切换到第二电阻状态来制造存储器单元阵列。 在一个实施例中，出厂切换操作可以包括弹出每个存储单元的反熔丝以使它们成为第二电阻状态。 将第二电阻状态的存储单元的阵列提供给终端用户。 控制电路还具有存储器阵列，其可以将所选择的单元的电阻切换回其初始电阻状态，以根据从用户或主机设备接收的数据对阵列进行编程。

公开(公告)号：US20080025066A1

公开(公告)日：2008-01-31

申请号：US11461339

申请日：2006-07-31

申请人： Luca G. Fasoli ,  Christopher J. Petti ,  Roy E. Scheuerlein

发明人： Luca G. Fasoli ,  Christopher J. Petti ,  Roy E. Scheuerlein

IPC分类号： G11C11/00

CPC分类号： G11C8/14

摘要： Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more thane one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.

摘要翻译： 描述了用于解码可编程的示例性存储器阵列的电路和方法，在一些实施例中，可重写无源元件存储器单元，其对于具有多于一个存储器平面的非常密集的三维存储器阵列特别有用。 此外，描述了用于选择这种存储器阵列的一个或多个阵列块的电路和方法，用于选择所选择的阵列块内的一个或多个字线和位线，用于将数据信息传送到选定的阵列块内的选定的存储器单元 并且用于将未选择的偏置条件传送到未选择的阵列块。

公开(公告)号：US07177227B2

公开(公告)日：2007-02-13

申请号：US11420787

申请日：2006-05-29

申请人： Christopher J. Petti ,  Roy E. Scheuerlein ,  Tanmay Kumar ,  Abhijit Bandyopadhyay

发明人： Christopher J. Petti ,  Roy E. Scheuerlein ,  Tanmay Kumar ,  Abhijit Bandyopadhyay

IPC分类号： G11C8/00 ,  G11C7/00

CPC分类号： G11C8/14 ,  G11C5/02 ,  G11C5/063 ,  G11C8/08 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/10894 ,  H01L27/10897

摘要： A multi-headed word line driver circuit incorporates bent-gate transistors to reduce the pitch otherwise achievable for interfacing to tightly-pitched array lines. In certain exemplary embodiments, a three-dimensional memory array includes multiple memory blocks and array lines traversing horizontally across at least one memory block. Vertical active area stripes are disposed beneath a first memory block, and a respective plurality of bent-gate electrodes intersects each respective active area stripe to define individual source/drain regions. Every other source/drain region is coupled to a bias node for the active area stripe, and remaining source/drain regions are respectively coupled to a respective array line associated with the first memory block, thereby forming a respective first driver transistor for the respective array line. In certain embodiments, a respective plurality of complementary array line driver circuits is disposed on each side of a connection area between adjacent memory blocks, and each such driver circuit is responsive to a single driver input node.

摘要翻译： 多头字线驱动电路包括弯栅晶体管，以减少为了与紧密排列的阵列线连接而实现的间距。 在某些示例性实施例中，三维存储器阵列包括穿过至少一个存储器块水平横越的多个存储器块和阵列线。 垂直有源区条纹设置在第一存储块下方，并且相应的多个弯曲栅电极与每个相应的有源区条纹相交以限定各个源/漏区。 每个其它源极/漏极区域耦合到用于有源区域条纹的偏置节点，并且剩余的源极/漏极区域分别耦合到与第一存储器模块相关联的相应阵列线，从而形成用于相应阵列的相应的第一驱动器晶体管 线。 在某些实施例中，相应的多个互补阵列线驱动器电路设置在相邻存储块之间的连接区域的每一侧上，并且每个这样的驱动器电路响应于单个驱动器输入节点。

公开(公告)号：US06888750B2

公开(公告)日：2005-05-03

申请号：US09927642

申请日：2001-08-13

申请人： Andrew J. Walker ,  Mark G. Johnson ,  N. Johan Knall ,  Igor G. Kouznetsov ,  Christopher J. Petti

发明人： Andrew J. Walker ,  Mark G. Johnson ,  N. Johan Knall ,  Igor G. Kouznetsov ,  Christopher J. Petti

IPC分类号： G11C16/04 ,  H01L21/77 ,  H01L21/8246 ,  H01L21/8247 ,  H01L21/84 ,  H01L27/06 ,  H01L27/102 ,  H01L27/115 ,  G11C5/02 ,  G11C16/00

CPC分类号： H01L27/11568 ,  G11C16/0466 ,  H01L21/822 ,  H01L21/8221 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11551 ,  H01L27/11578

摘要： A nonvolatile memory array is provided. The array includes an array of nonvolatile memory devices, at least one driver circuit, and a substrate. The at least one driver circuit is not located in a bulk monocrystalline silicon substrate. The at least one driver circuit may be located in a silicon on insulator substrate or in a compound semiconductor substrate.

摘要翻译： 提供非易失性存储器阵列。 阵列包括非易失性存储器件阵列，至少一个驱动器电路和衬底。 至少一个驱动电路不位于大块单晶硅衬底中。 至少一个驱动电路可以位于绝缘体上硅衬底或化合物半导体衬底中。

公开(公告)号：US06784552B2

公开(公告)日：2004-08-31

申请号：US09540610

申请日：2000-03-31

申请人： James E. Nulty ,  Christopher J. Petti

发明人： James E. Nulty ,  Christopher J. Petti

IPC分类号： H01L2348

CPC分类号： H01L21/76897 ,  H01L21/31116 ,  H01L21/76838 ,  H01L21/823425 ,  H01L21/823475

摘要： A process for minimizing lateral spacer erosion of an insulating layer adjacent to a contact region and an apparatus whereby there is provided a contact opening with a small alignment tolerance relative to a gate electrode or other structure are disclosed. The process includes the steps of forming a conductive layer on a semiconductor body, then depositing an insulating layer adjacent to the conductive layer. Next, substantially rectangular insulating spacers are formed adjacent to the gate electrode. An etch stop layer is deposited adjacent the insulating layer, followed by an etch to remove the etch stop layer material from the contact region. This etch is conducted under conditions wherein the etch removes the etch stop layer, but retains the substantially rectangular lateral spacer profile of the first insulating layer. The apparatus is capable of maintaining high quality contacts between the conductive material in the contact region and an underlying device region such as a source or drain, or some other layer or structure, and is an effective structure for small feature size structures, particularly self-aligned contact structures.

摘要翻译： 公开了一种使邻近接触区域的绝缘层的横向间隔物侵蚀最小化的方法以及相对于栅电极或其他结构提供具有小对准公差的接触开口的装置。 该方法包括以下步骤：在半导体本体上形成导电层，然后沉积与导电层相邻的绝缘层。 接下来，与栅电极相邻地形成大致矩形的绝缘间隔物。 在绝缘层附近沉积蚀刻停止层，随后进行蚀刻以从接触区域去除蚀刻停止层材料。 该蚀刻在其中蚀刻去除蚀刻停止层但保留第一绝缘层的基本上矩形的横向间隔物轮廓的条件下进行。 该装置能够在接触区域中的导电材料和诸如源极或漏极或其它一些层或结构的下面的器件区域之间保持高质量的接触，并且是小尺寸特征结构的有效结构， 对齐的接触结构。

公开(公告)号：US08741696B2

公开(公告)日：2014-06-03

申请号：US12911944

申请日：2010-10-26

申请人： Roy E. Scheuerlein ,  Christopher J. Petti ,  Yoichiro Tanaka

发明人： Roy E. Scheuerlein ,  Christopher J. Petti ,  Yoichiro Tanaka

IPC分类号： H01L21/82

CPC分类号： G11C5/06 ,  H01L21/0337 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/2481 ,  H01L2924/0002 ,  Y10S257/909 ,  H01L2924/00

摘要： The present invention provides apparatus, methods, and systems for fabricating memory structures methods of forming pillars for memory cells using sequential sidewall patterning. The invention includes forming first features from a first template layer disposed above a memory layer stack; forming first sidewall spacers adjacent the first features; forming second features that extend in a first direction in a mask layer by using the first sidewall spacers as a hardmask; depositing a second template layer on the mask layer; forming third features from the second template layer; forming second sidewall spacers adjacent the third features; and forming fourth features that extend in a second direction in the mask layer by using the second sidewall spacers as a hardmask. Numerous additional aspects are disclosed.

摘要翻译： 本发明提供用于制造存储器结构的装置，方法和系统，该方法使用顺序侧壁图案化形成用于存储单元的支柱。 本发明包括从设置在存储层堆叠上方的第一模板层形成第一特征; 形成邻近所述第一特征的第一侧壁间隔物; 通过使用第一侧壁间隔物作为硬掩模形成在掩模层中沿第一方向延伸的第二特征; 在掩模层上沉积第二模板层; 从第二模板层形成第三特征; 形成邻近所述第三特征的第二侧壁间隔物; 并且通过使用第二侧壁间隔件作为硬掩模形成在掩模层中沿第二方向延伸的第四特征。 公开了许多附加方面。

公开(公告)号：US20130203205A1

公开(公告)日：2013-08-08

申请号：US13425877

申请日：2012-03-21

申请人： Venkatesan Murali ,  Arvind Chari ,  Gopal Prabhu ,  Christopher J. Petti

发明人： Venkatesan Murali ,  Arvind Chari ,  Gopal Prabhu ,  Christopher J. Petti

IPC分类号： H01L31/0232

CPC分类号： H01L27/14632 ,  H01L21/6835 ,  H01L27/1464 ,  H01L27/14687 ,  H01L31/103 ,  H01L31/1896 ,  Y02E10/50

摘要： A method for fabricating a backside-illuminated sensor includes providing a thin film semiconductor lamina having a first conductivity, and forming a doped region having a second conductivity within the lamina and at a front surface of the lamina. The lamina may be provided as a free-standing lamina, or may be provided as a semiconductor donor body from which the lamina is cleaved. An electrical connection is formed to the doped region. A temporary carrier is contacted to the back surface of the semiconductor and later removed. A backside-illuminated sensor is fabricated from the semiconductor lamina, in which the thickness of the semiconductor lamina remains substantially unchanged during the fabrication process.

摘要翻译： 一种用于制造背面照射传感器的方法包括提供具有第一导电性的薄膜半导体薄片，以及在薄层内和薄片的前表面处形成具有第二导电性的掺杂区域。 层可以提供为独立的层，或者可以提供为半导体施主体，层从其中被切割。 与掺杂区形成电连接。 临时载体与半导体的后表面接触并稍后移除。 背面照明的传感器由半导体层制成，其中半导体层的厚度在制造过程中保持基本上不变。