公开(公告)号：US09450614B2

公开(公告)日：2016-09-20

申请号：US14475619

申请日：2014-09-03

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Scott C. Best

IPC: H03M13/15 ,  H03M13/00 ,  G06F11/10 ,  H03M13/53

CPC classification number: G06F11/1048 ,  H03M13/1525 ,  H03M13/19 ,  H03M13/617

Abstract: A memory system includes a memory module that supports error detection and correction (EDC) in a manner that relieves a memory controller or processor of some or all of the computational burden associated with EDC. Individual EDC components perform EDC functions on subsets of the data, and share data between themselves using relatively short, fast interconnections.

Abstract translation: 存储器系统包括以能够缓解存储器控制器或处理器与EDC相关联的一些或全部计算负担的方式支持错误检测和校正（EDC）的存储器模块。 单独的EDC组件在数据子集上执行EDC功能，并使用相对较短，快速的互连在其间共享数据。

公开(公告)号：US20160125929A1

公开(公告)日：2016-05-05

申请号：US14849425

申请日：2015-09-09

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  Richard E. Warmke ,  David B. Roberts ,  Frank Lambrecht

IPC: G11C11/4076

CPC classification number: G11C11/4076 ,  G06F1/10 ,  G11C7/04 ,  G11C7/10 ,  G11C7/1087 ,  G11C7/222 ,  G11C11/4091 ,  G11C2207/107 ,  H03L7/07 ,  H03L7/0814 ,  H04L7/0337

Abstract: A memory controller receives data and phase-providing signals from a memory device. The phase-providing signal is not a clock signal, but is used by the memory controller to phase align a local data-sampling signal with the incoming data. The memory controller samples the data signal with the data-sampling signal. The memory controller can perform maintenance operations to update the phase relationship between the phase-providing and data-sampling signals.

公开(公告)号：US20150363107A1

公开(公告)日：2015-12-17

申请号：US14737147

申请日：2015-06-11

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  Frederick A. Ware ,  William N. Ng

IPC: G06F3/06 ,  G06F12/08

CPC classification number: G11C7/1093 ,  G11C5/04 ,  G11C7/1003 ,  G11C7/1066

Abstract: A memory module can be programmed to deliver relatively wide, low-latency data in a first access mode, or to sacrifice some latency in return for a narrower data width, a narrower command width, or both, in a second access mode. The narrow, higher-latency mode requires fewer connections and traces. A controller can therefore support more modules, and thus increased system capacity. Programmable modules thus allow computer manufacturers to strike a desired balance between memory latency, capacity, and cost.

Abstract translation: 存储器模块可以被编程为在第一访问模式下提供相对宽的，低延迟的数据，或者在第二访问模式中牺牲一些延迟，以换取较窄的数据宽度，较窄的命令宽度或两者。 窄的，更高延迟的模式需要更少的连接和跟踪。 因此，控制器可以支持更多的模块，从而增加系统容量。 因此可编程模块允许计算机制造商在存储器延迟，容量和成本之间达到期望的平衡。

公开(公告)号：US20140293725A1

公开(公告)日：2014-10-02

申请号：US14306174

申请日：2014-06-16

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  Ely Tsern

IPC: G11C11/406

CPC classification number: G11C11/406 ,  G06F13/1636 ,  G11C2211/4061

Abstract: An apparatus is disclosed that includes a memory controller chip and memory chips packaged with the memory controller chip. Each memory chip includes normal-retention storage rows that exhibit retention times greater or equal to a first time interval, and having been tested to generate information identifying low-retention storage rows that exhibit retention times less than the first time interval. Refresh logic refreshes the normal-retention storage rows at a first refresh rate corresponding to the first time interval, and refreshes each low-retention storage row at a second refresh rate that is greater than the first refresh rate.

Abstract translation: 公开了一种包括与存储器控制器芯片封装的存储器控​​制器芯片和存储器芯片的装置。 每个存储器芯片包括呈现大于或等于第一时间间隔的保持时间的正常保留存储行，并且已经被测试以生成标识低保留存储行的信息，其表现出小于第一时间间隔的保留时间。 刷新逻辑以对应于第一时间间隔的第一刷新速率刷新正常保留存储行，并且以大于第一刷新率的第二刷新率刷新每个低保留存储行。

公开(公告)号：US20140068169A1

公开(公告)日：2014-03-06

申请号：US13923184

申请日：2013-06-20

Applicant: Rambus Inc.

Inventor： Frederick Ware ,  Craig E. Hampel ,  Ian Shaeffer ,  Scott C. Best

IPC: G11C7/10

CPC classification number: G11C7/1072 ,  G06F13/1684 ,  G06F13/4234 ,  G11C5/00

Abstract: A memory module includes a substrate having signal lines thereon that form a control path and a plurality of data paths. A plurality of memory devices are mounted on the substrate. Each memory device is coupled to the control path and to a distinct data path. The memory module includes control circuitry to enable each memory device to process a distinct respective memory access command in a succession of memory access commands and to output data on the distinct data path in response to the processed memory access command.

Abstract translation: 存储器模块包括其上具有信号线的衬底，其形成控制路径和多个数据路径。 多个存储器件安装在基片上。 每个存储器件耦合到控制路径和不同的数据路径。 存储器模块包括控制电路，以使得每个存储器设备能够在一系列存储器访问命令中处理不同的相应存储器访问命令，并且响应于处理的存储器访问命令在不同的数据路径上输出数据。

公开(公告)号：US20240404580A1

公开(公告)日：2024-12-05

申请号：US18657631

申请日：2024-05-07

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  Ming Li

IPC: G11C11/4093 ,  G11C5/02 ,  G11C5/04 ,  G11C11/406 ,  G11C11/4096 ,  H01L23/00 ,  H01L23/48 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18

Abstract: A memory is disclosed that includes a logic die having first and second memory interface circuits. A first memory die is stacked with the logic die, and includes first and second memory arrays. The first memory array couples to the first memory interface circuit. The second memory array couples to the second interface circuit. A second memory die is stacked with the logic die and the first memory die. The second memory die includes third and fourth memory arrays. The third memory array couples to the first memory interface circuit. The fourth memory array couples to the second memory interface circuit. Accesses to the first and third memory arrays are carried out independently from accesses to the second and fourth memory arrays.

公开(公告)号：US20240257846A1

公开(公告)日：2024-08-01

申请号：US18584434

申请日：2024-02-22

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  Frederick A. Ware ,  William N. Ng

IPC: G11C7/10 ,  G11C5/04

CPC classification number: G11C7/1093 ,  G11C5/04 ,  G11C7/1003 ,  G11C7/1066

Abstract: A memory module can be programmed to deliver relatively wide, low-latency data in a first access mode, or to sacrifice some latency in return for a narrower data width, a narrower command width, or both, in a second access mode. The narrow, higher-latency mode requires fewer connections and traces. A controller can therefore support more modules, and thus increased system capacity. Programmable modules thus allow computer manufacturers to strike a desired balance between memory latency, capacity, and cost.

公开(公告)号：US20240111457A1

公开(公告)日：2024-04-04

申请号：US18496887

申请日：2023-10-29

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Scott C. Best

IPC: G06F3/06 ,  G06F13/16 ,  G11C5/04

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0629 ,  G06F3/0673 ,  G06F13/1673 ,  G11C5/04 ,  Y02D10/00

Abstract: A memory module with multiple memory devices includes a buffer system that manages communication between a memory controller and the memory devices. The memory module additionally includes a command input port to receive command and address signals from a controller and, also in support of capacity extensions, a command relay circuit coupled to the command port to convey the commands and addresses from the memory module to another module or modules. Relaying commands and addresses introduces a delay, and the buffer system that manages communication between the memory controller and the memory devices can be configured to time data communication to account for that delay.

公开(公告)号：US11942182B2

公开(公告)日：2024-03-26

申请号：US18089668

申请日：2022-12-28

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  Frederick A. Ware ,  William N. Ng

IPC: G11C7/10 ,  G11C5/04

CPC classification number: G11C7/1093 ,  G11C5/04 ,  G11C7/1003 ,  G11C7/1066

Abstract: A memory module can be programmed to deliver relatively wide, low-latency data in a first access mode, or to sacrifice some latency in return for a narrower data width, a narrower command width, or both, in a second access mode. The narrow, higher-latency mode requires fewer connections and traces. A controller can therefore support more modules, and thus increased system capacity. Programmable modules thus allow computer manufacturers to strike a desired balance between memory latency, capacity, and cost.

公开(公告)号：US20240079079A1

公开(公告)日：2024-03-07

申请号：US18233257

申请日：2023-08-11

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  John Eric Linstadt ,  Paul William Roukema

IPC: G11C29/44 ,  G11C5/04 ,  G11C11/401 ,  G11C29/00 ,  G11C29/02 ,  G11C29/52

CPC classification number: G11C29/4401 ,  G11C5/04 ,  G11C11/401 ,  G11C29/022 ,  G11C29/52 ,  G11C29/76 ,  G11C29/783 ,  G11C29/88 ,  G11C2029/4402

Abstract: A buffer circuit is disclosed. The buffer circuit includes a command address (C/A) interface to receive an incoming activate (ACT) command and an incoming column address strobe (CAS) command. A first match circuit includes first storage to store failure row address information associated with the memory, and first compare logic. The first compare logic is responsive to the ACT command, to compare incoming row address information to the stored failure row address information. A second match circuit includes second storage to store failure column address information associated with the memory, and second compare logic. The second compare logic is responsive to the CAS command, to compare the incoming column address information to the stored failure column address information. Gating logic maintains a state of a matching row address identified by the first compare logic during the comparison carried out by the second compare logic.