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61.发明申请NON-PLANAR SEMICONDUCTOR DEVICE HAVING GROUP III-V MATERIAL ACTIVE REGION WITH MULTI-DIELECTRIC GATE STACK 审中-公开具有多层电极堆叠的III-V族材料活性区域的非平面半导体器件公开(公告)号：US20150221762A1
公开(公告)日：2015-08-06
申请号：US14688410
申请日：2015-04-16
IPC分类号： H01L29/78 , H01L29/06 , H01L29/423 , H01L29/201 , H01L29/51
CPC分类号： H01L29/0673 , B82Y10/00 , B82Y99/00 , H01L29/0665 , H01L29/201 , H01L29/205 , H01L29/408 , H01L29/4236 , H01L29/42364 , H01L29/42392 , H01L29/511 , H01L29/512 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66462 , H01L29/775 , H01L29/78 , H01L29/785 , H01L29/78696
摘要： Non-planar semiconductor devices having group III-V material active regions with multi-dielectric gate stacks are described. For example, a semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a three-dimensional group III-V material body with a channel region. A source and drain material region is disposed above the three-dimensional group III-V material body. A trench is disposed in the source and drain material region separating a source region from a drain region, and exposing at least a portion of the channel region. A gate stack is disposed in the trench and on the exposed portion of the channel region. The gate stack includes first and second dielectric layers and a gate electrode.
摘要翻译： 描述具有多电介质栅叠层的具有III-V族材料的区域的非平面半导体器件。 例如，半导体器件包括设置在衬底上的异质结构。 异质结构包括具有沟道区的三维III-V族材料体。 源极和漏极材料区域设置在三维III-V族材料体上方。 在源极和漏极材料区域中布置沟槽，其将源极区域与漏极区域分离，并且暴露沟道区域的至少一部分。 栅极堆叠设置在沟槽中和沟道区域的暴露部分上。 栅极堆叠包括第一和第二电介质层和栅电极。
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62.发明授权Self-aligned structures and methods for asymmetric GaN transistors and enhancement mode operation 有权用于非对称GaN晶体管的自对准结构和方法以及增强模式操作公开(公告)号：US09099490B2
公开(公告)日：2015-08-04
申请号：US13631534
申请日：2012-09-28
申请人： Sansaptak Dasgupta , Han Wui Then , Marko Radosavljevic , Niloy Mukherjee , Niti Goel , Sanaz Kabehie , Seung Hoon Sung , Ravi Pillarisetty , Robert S. Chau
发明人： Sansaptak Dasgupta , Han Wui Then , Marko Radosavljevic , Niloy Mukherjee , Niti Goel , Sanaz Kabehie , Seung Hoon Sung , Ravi Pillarisetty , Robert S. Chau
IPC分类号： H01L29/66 , H01L29/778 , H01L29/423 , H01L29/08 , H01L29/20
CPC分类号： H01L29/7784 , H01L21/0254 , H01L21/2233 , H01L21/2236 , H01L21/2654 , H01L21/26546 , H01L21/31111 , H01L21/31144 , H01L29/0847 , H01L29/2003 , H01L29/205 , H01L29/207 , H01L29/42376 , H01L29/66462 , H01L29/7786 , H01L29/7787
摘要： Embodiments include high electron mobility transistors (HEMT). In embodiments, a gate electrode is spaced apart by different distances from a source and drain semiconductor region to provide high breakdown voltage and low on-state resistance. In embodiments, self-alignment techniques are applied to form a dielectric liner in trenches and over an intervening mandrel to independently define a gate length, gate-source length, and gate-drain length with a single masking operation. In embodiments, III-N HEMTs include fluorine doped semiconductor barrier layers for threshold voltage tuning and/or enhancement mode operation.
摘要翻译： 实施例包括高电子迁移率晶体管（HEMT）。 在实施例中，栅电极与源极和漏极半导体区间隔开不同的距离以提供高击穿电压和低导通状态电阻。 在实施例中，应用自对准技术以在沟槽中和在中间心轴上形成电介质衬垫，以通过单个掩蔽操作独立地限定栅极长度，栅极源长度和栅极 - 漏极长度。 在实施例中，III-N HEMT包括用于阈值电压调谐和/或增强模式操作的氟掺杂半导体势垒层。
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公开(公告)号：US08344425B2
公开(公告)日：2013-01-01
申请号：US12655463
申请日：2009-12-30
申请人： Marko Radosavljevic , Uday Shah , Gilbert Dewey , Niloy Mukherjee , Robert S. Chau , Jack Kavalieros , Ravi Pillarisetty , Titash Rakshit , Matthew V. Metz
发明人： Marko Radosavljevic , Uday Shah , Gilbert Dewey , Niloy Mukherjee , Robert S. Chau , Jack Kavalieros , Ravi Pillarisetty , Titash Rakshit , Matthew V. Metz
IPC分类号： H01L29/12 , H01L21/20 , H01L21/336 , H01L21/18
CPC分类号： H01L29/0665 , B82Y10/00 , B82Y40/00 , H01L29/0673 , H01L29/42364 , H01L29/66462 , H01L29/66795 , H01L29/7786 , H01L29/785
摘要： Methods of forming microelectronic structures are described. Embodiments of those methods include forming a III-V tri-gate fin on a substrate, forming a cladding material around the III-V tri-gate fin, and forming a hi k gate dielectric around the cladding material.
摘要翻译： 描述形成微电子结构的方法。 这些方法的实施例包括在基板上形成III-V三栅极翅片，在III-V三栅极鳍周围形成包层材料，以及在包层材料周围形成Hi栅极电介质。
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公开(公告)号：US20110156004A1
公开(公告)日：2011-06-30
申请号：US12655463
申请日：2009-12-30
申请人： Marko Radosavljevic , Uday Shah , Gilbert Dewey , Niloy Mukherjee , Robert S. Chau , Jack Kavalieros , Ravi Pillarisetty , Titash Rakshit , Matthew V. Metz
发明人： Marko Radosavljevic , Uday Shah , Gilbert Dewey , Niloy Mukherjee , Robert S. Chau , Jack Kavalieros , Ravi Pillarisetty , Titash Rakshit , Matthew V. Metz
IPC分类号： H01L29/775 , H01L21/20 , H01L21/336
CPC分类号： H01L29/0665 , B82Y10/00 , B82Y40/00 , H01L29/0673 , H01L29/42364 , H01L29/66462 , H01L29/66795 , H01L29/7786 , H01L29/785
摘要： Methods of forming microelectronic structures are described. Embodiments of those methods include forming a III-V tri-gate fin on a substrate, forming a cladding material around the III-V tri-gate fin, and forming a hi k gate dielectric around the cladding material.
摘要翻译： 描述形成微电子结构的方法。 这些方法的实施例包括在基板上形成III-V三栅极翅片，在III-V三栅极鳍周围形成包层材料，以及在包层材料周围形成Hi栅极电介质。
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65.发明申请METHODS OF FORMING HETERO-LAYERS WITH REDUCED SURFACE ROUGHNESS AND BULK DEFECT DENSITY ON NON-NATIVE SURFACES AND THE STRUCTURES FORMED THEREBY 有权形成具有减少的表面粗糙度和非局部表面上的体积密度的异质层的方法及其形成的结构公开(公告)号：US20140203326A1
公开(公告)日：2014-07-24
申请号：US13997607
申请日：2011-12-28
申请人： Niloy Mukherjee , Matthew V. Metz , james m. Powers , Van H. Le , Benjamin Chu-Kung , Mark R. Lemay , Marko Radosavljevic , Niti Goel
发明人： Niloy Mukherjee , Matthew V. Metz , james m. Powers , Van H. Le , Benjamin Chu-Kung , Mark R. Lemay , Marko Radosavljevic , Niti Goel
CPC分类号： H01L29/06 , H01L21/0237 , H01L21/0245 , H01L21/02455 , H01L21/02494 , H01L21/02502 , H01L21/02505 , H01L21/0251 , H01L21/02513 , H01L21/02532 , H01L21/02538 , H01L21/02587 , H01L21/0259 , H01L21/02617 , H01L21/02636 , H01L21/02658 , H01L21/02664
摘要： Methods of forming hetero-layers with reduced surface roughness and bulk defect density on non-native surfaces and the devices formed thereby are described. In one embodiment, the method includes providing a substrate having a top surface with a lattice constant and depositing a first layer on the top surface of the substrate. The first layer has a top surface with a lattice constant that is different from the first lattice constant of the top surface of the substrate. The first layer is annealed and polished to form a polished surface. A second layer is then deposited above the polished surface.
摘要翻译： 描述了在非天然表面上形成具有降低的表面粗糙度和体缺陷密度的异质层以及由此形成的器件的方法。 在一个实施例中，该方法包括提供具有晶格常数的顶表面并在衬底的顶表面上沉积第一层的衬底。 第一层具有不同于衬底顶表面的第一晶格常数的晶格常数的顶表面。 第一层被退火和抛光以形成抛光表面。 然后在抛光表面上方沉积第二层。
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公开(公告)号：US08890118B2
公开(公告)日：2014-11-18
申请号：US12972057
申请日：2010-12-17
IPC分类号： H01L29/06 , H01L29/08 , H01L29/739
CPC分类号： H01L29/7391 , H01L29/0843
摘要： The present disclosure relates to the field of microelectronic transistor fabrication and, more particularly, to the fabrication of a tunnel field effect transistor having an improved on-current level without a corresponding increasing the off-current level, achieved by the addition of a transition layer between a source and an intrinsic channel of the tunnel field effect transistor.
摘要翻译： 本公开涉及微电子晶体管制造领域，更具体地说，涉及具有改善的导通电流水平的隧道场效应晶体管的制造，而不相应地增加截止电流水平，通过添加过渡层 在隧道场效应晶体管的源极和固有通道之间。
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公开(公告)号：US20120153352A1
公开(公告)日：2012-06-21
申请号：US12968905
申请日：2010-12-15
IPC分类号： H01L29/778
CPC分类号： H01L29/78696 , H01L29/20
摘要： The present disclosure relates to the field of microelectronic transistor fabrication and, more particularly, to the formation of high mobility transistor channels from high indium content alloys, wherein the high indium content transistor channels are achieved with a barrier layer that can substantially lattice match with the high indium content transistor channel.
摘要翻译： 本公开内容涉及微电子晶体管制造领域，更具体地涉及从高铟含量合金形成高迁移率晶体管沟道，其中高铟含量晶体管沟道通过阻挡层实现，该阻挡层基本上可以与 高铟含量晶体管通道。
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公开(公告)号：US20130240838A1
公开(公告)日：2013-09-19
申请号：US13872966
申请日：2013-04-29
IPC分类号： H01L29/778 , H01L29/66
CPC分类号： H01L29/7783 , B82Y10/00 , H01L29/66431 , H01L29/66462 , H01L29/778 , H01L29/7781 , H01L29/7782 , H01L29/7785 , H01L29/7848 , H01L29/802 , H01L29/803
摘要： Embodiments of the present disclosure describe structures and techniques to increase carrier injection velocity for integrated circuit devices. An integrated circuit device includes a semiconductor substrate, a first barrier film coupled with the semiconductor substrate, a quantum well channel coupled to the first barrier film, the quantum well channel comprising a first material having a first bandgap energy, and a source structure coupled to launch mobile charge carriers into the quantum well channel, the source structure comprising a second material having a second bandgap energy, wherein the second bandgap energy is greater than the first bandgap energy. Other embodiments may be described and/or claimed.
摘要翻译： 本公开的实施例描述了用于增加集成电路器件的载流子注入速度的结构和技术。 集成电路器件包括半导体衬底，与半导体衬底耦合的第一阻挡膜，耦合到第一阻挡膜的量子阱沟道，该量子阱沟道包括具有第一带隙能量的第一材料和耦合到 将移动电荷载流子发射到量子阱沟道中，源结构包括具有第二带隙能量的第二材料，其中第二带隙能量大于第一带隙能量。 可以描述和/或要求保护其他实施例。
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公开(公告)号：US08440998B2
公开(公告)日：2013-05-14
申请号：US12643848
申请日：2009-12-21
IPC分类号： H01L29/06
CPC分类号： H01L29/7783 , B82Y10/00 , H01L29/66431 , H01L29/66462 , H01L29/778 , H01L29/7781 , H01L29/7782 , H01L29/7785 , H01L29/7848 , H01L29/802 , H01L29/803
摘要： Embodiments of the present disclosure describe structures and techniques to increase carrier injection velocity for integrated circuit devices. An integrated circuit device includes a semiconductor substrate, a first barrier film coupled with the semiconductor substrate, a quantum well channel coupled to the first barrier film, the quantum well channel comprising a first material having a first bandgap energy, and a source structure coupled to launch mobile charge carriers into the quantum well channel, the source structure comprising a second material having a second bandgap energy, wherein the second bandgap energy is greater than the first bandgap energy. Other embodiments may be described and/or claimed.
摘要翻译： 本公开的实施例描述了用于增加集成电路器件的载流子注入速度的结构和技术。 集成电路器件包括半导体衬底，与半导体衬底耦合的第一阻挡膜，耦合到第一阻挡膜的量子阱沟道，该量子阱沟道包括具有第一带隙能量的第一材料和耦合到 将移动电荷载流子发射到量子阱沟道中，源结构包括具有第二带隙能量的第二材料，其中第二带隙能量大于第一带隙能量。 可以描述和/或要求保护其他实施例。
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公开(公告)号：US20120153263A1
公开(公告)日：2012-06-21
申请号：US12972057
申请日：2010-12-17
IPC分类号： H01L29/15
CPC分类号： H01L29/7391 , H01L29/0843
摘要： The present disclosure relates to the field of microelectronic transistor fabrication and, more particularly, to the fabrication of a tunnel field effect transistor having an improved on-current level without a corresponding increasing the off-current level, achieved by the addition of a transition layer between a source and an intrinsic channel of the tunnel field effect transistor.
摘要翻译： 本公开涉及微电子晶体管制造领域，更具体地说，涉及具有改善的导通电流水平的隧道场效应晶体管的制造，而不相应地增加截止电流水平，通过添加过渡层 在隧道场效应晶体管的源极和固有沟道之间。
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