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61.发明授权Circuit and method for formatting each of a series of encoded video images into respective regions 有权将一系列编码视频图像中的每一个格式化成相应区域的电路和方法公开(公告)号：US06498816B1
公开(公告)日：2002-12-24
申请号：US09390239
申请日：1999-09-03
IPC分类号： H04B166
摘要： A video processing circuit includes a processor that receives encoded images each having respective first and second regions and that receives a motion vector of the first region of a first one of the images. If the motion vector points to the second region of an image, the processor re-encodes at least a portion of the first region of the first image such that the first region of the first image has no motion vector that points to the second region of an image.
摘要翻译： 视频处理电路包括接收编码图像的处理器，每个编码图像具有相应的第一和第二区域，并且接收第一个图像的第一区域的运动矢量。 如果运动矢量指向图像的第二区域，则处理器重新编码第一图像的第一区域的至少一部分，使得第一图像的第一区域没有指向第二区域的运动矢量 一个图像。
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62.发明授权Single integrated circuit embodying a risc processor and a digital signal processor 失效单个集成电路体现了一个risc处理器和一个数字信号处理器公开(公告)号：US06260088B1
公开(公告)日：2001-07-10
申请号：US09517990
申请日：2000-03-03
IPC分类号： G06F1300
CPC分类号： G06F15/17375
摘要： A single integrated circuit includes first and second data processors operating on different instruction sets independently operating on disjoint programs and data. The single integrated circuit preferably includes an external interface, a shared data transfer controller and shared memory divided into plural independently accessible memory banks. The two data processors are preferably a digital signal processor (DSP) and a reduced instruction set computer (RISC) processor. The DSP and RISC processors are suitably programmed to perform differing aspects of computer image processing.
摘要翻译： 单个集成电路包括在不相交的程序和数据上独立操作的不同指令集上操作的第一和第二数据处理器。 单个集成电路优选地包括外部接口，共享数据传输控制器和被分成多个可独立存取的存储体的共享存储器。 两个数据处理器优选地是数字信号处理器（DSP）和精简指令集计算机（RISC）处理器。 DSP和RISC处理器被适当地编程以执行计算机图像处理的不同方面。
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公开(公告)号：US6116768A
公开(公告)日：2000-09-12
申请号：US160299
申请日：1993-11-30
申请人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Phillip Moyse
发明人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Phillip Moyse
CPC分类号： G06F9/30014 , G06F12/0284 , G06F5/015 , G06F9/30018 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/30094 , G06F9/30167 , G06F9/325
摘要： A data processing apparatus includes a three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. Data registers (200) store the three data inputs and the arithmetic logic unit output. The second input signal comes from a controllable barrel rotator (235). The rotate amount is a default rotate amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the barrel rotator (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the rotate amount. The output of the barrel rotator (235) may be stored independently of the arithmetic logic unit (230) result. In the preferred embodiment of this invention, the three input arithmetic logic unit (230) is embodied in a data processor circuits as a part of a multiprocessor integrated circuit (100) used in image processing.
摘要翻译： 数据处理装置包括产生由功能信号选择的三个输入的组合的三输入算术逻辑单元（230）。 数据寄存器（200）存储三个数据输入和算术逻辑单元输出。 第二输入信号来自可控筒旋转器（235）。 旋转量是存储在特殊数据寄存器中的默认旋转量，从数据寄存器或零调用的预定数据位组。 恒定源（236）连接到筒旋转器（235）以提供“1”的多位数字信号。 这允许产生形式2N的第二输入信号，其中N是旋转量。 桶旋转器（235）的输出可以独立于算术逻辑单元（230）的结果存储。 在本发明的优选实施例中，三输入算术逻辑单元（230）被实现为作为在图像处理中使用的多处理器集成电路（100）的一部分的数据处理器电路。
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64.发明授权System and method of memory access in apparatus having plural processors and plural memories 失效具有多个处理器和多个存储器的设备中的存储器访问的系统和方法
公开(公告)号：US6070003A
公开(公告)日：2000-05-30
申请号：US264582
申请日：1994-06-22
IPC分类号： G06F15/173 , G06F13/16
CPC分类号： G06F15/17375
摘要： There is disclosed a multi-processor system and method arranged, in one embodiment, as an image and graphics processor. The image processor is structured with several individual processors all having communication links to several memories. A crossbar switch serves to establish the processor memory links. The entire image processor, including the individual processors, the crossbar switch and the memories, is contained on a single silicon chip.
摘要翻译： 已经公开了在一个实施例中将图像处理器和图形处理器设置为多处理器系统和方法。 图像处理器被构造成具有几个单独的处理器，它们都具有到几个存储器的通信链路。 交叉开关用于建立处理器存储器链路。 整个图像处理器（包括各个处理器，交叉开关和存储器）都包含在单个硅芯片上。
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65.发明授权
公开(公告)号：US5961635A
公开(公告)日：1999-10-05
申请号：US160111
申请日：1993-11-30
申请人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Phillip Moyse
发明人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Phillip Moyse
摘要： A three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. The second input signal comes from a controllable barrel rotator (235). The rotate amount is a default rotate amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the barrel rotator (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the rotate amount. The output of the barrel rotator (235) may be stored independently of the arithmetic logic unit (230) result. The third input signal comes from a multiplexer (233) that selects between an instruction specified immediate field, data recalled from a data register or a mask input from a mask generator (239). One preferred form of the mask has a number of right justified 1's corresponding to a mask input signal. This mask input signal may be the default barrel rotate amount or a predetermined number of the least significant bits of a third input signal as selected by a multiplexer. A second preferred form of the mask is selected one of the left most 1, the right most 1, the left most bit change or the right most bit change of a predetermined set of the least significant bits of data recalled from a data register.
摘要翻译： 三输入算术逻辑单元（230），其生成由功能信号选择的三个输入的组合。 第二输入信号来自可控筒旋转器（235）。 旋转量是存储在特殊数据寄存器中的默认旋转量，从数据寄存器或零调用的预定数据位组。 恒定源（236）连接到筒旋转器（235）以提供“1”的多位数字信号。 这允许产生形式2N的第二输入信号，其中N是旋转量。 桶旋转器（235）的输出可以独立于算术逻辑单元（230）的结果存储。 第三输入信号来自多路复用器（233），其在指定的指令字段，从数据寄存器调用的数据或从掩码生成器输入的掩码（239）之间进行选择。 掩模的一个优选形式具有对应于掩模输入信号的许多右对齐1。 该掩模输入信号可以是由多路复用器选择的默认桶旋转量或第三输入信号的预定数量的最低有效位。 选择掩模的第二优选形式是从数据寄存器回调的数据的最低有效位的预定集合的最左1，最右1，最左位变化或最右位变化中的一个。
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66.发明授权Base address generation in a multi-processing system having plural memories with a unified address space corresponding to each processor 失效在具有与每个处理器对应的统一地址空间的多个存储器的多处理系统中产生基地址
公开(公告)号：US5761726A
公开(公告)日：1998-06-02
申请号：US479981
申请日：1995-06-07
申请人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Philip Moyse
发明人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Philip Moyse
CPC分类号： G06F9/30014 , G06F12/0284 , G06F5/015 , G06F9/30018 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/30094 , G06F9/30167 , G06F9/325
摘要： A multi-processing system includes a plurality of memories and a plurality of processors. Each of the memories has a unique addressable memory portion of a single memory address space. Each processors has a predetermined plurality of corresponding memories. These corresponding memories have a corresponding base address within said single memory address space The processors generate addresses for read/write access to data stored within said plurality of memories in accordance with received instructions. A switch matrix connected to the memories and the processors responds to an address generated by a processor to selectively route data between that processor and a memories whose unique addressable memory portion encompasses that address. A base address instruction executing on any one of the processors generates the base address corresponding to that processor. The base address preferably is substituted for the contents of a base address register in an address unit including a set of base address registers, a set of index address registers and a full adder.
摘要翻译： 多处理系统包括多个存储器和多个处理器。 每个存储器具有单个存储器地址空间的唯一可寻址存储器部分。 每个处理器具有预定的多个对应的存储器。 这些相应的存储器在所述单个存储器地址空间内具有对应的基址。根据接收到的指令，处理器产生用于对存储在所述多个存储器中的数据进行读/写访问的地址。 连接到存储器和处理器的开关矩阵响应由处理器产生的地址，以选择性地在该处理器与其唯一可寻址存储器部分包含该地址的存储器之间路由数据。 在任一个处理器上执行的基地址指令产生与该处理器对应的基地址。 基址优选地代替包括一组基地址寄存器，一组索引地址寄存器和全加器的地址单元中的基地址寄存器的内容。
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67.发明授权Data processor having capability to perform both floating point operations and memory access in response to a single instruction 失效数据处理器具有响应于单个指令执行浮点运算和存储器访问的能力
公开(公告)号：US5673407A
公开(公告)日：1997-09-30
申请号：US207987
申请日：1994-03-08
申请人： Sydney W. Poland , Christopher J. Read , Karl M. Guttag , Robert J. Gove , Michael Gill , Nicholas Ing Simmons , Erick Oakland , Jeremiah E. Golston
发明人： Sydney W. Poland , Christopher J. Read , Karl M. Guttag , Robert J. Gove , Michael Gill , Nicholas Ing Simmons , Erick Oakland , Jeremiah E. Golston
CPC分类号： G06F5/012 , G06F9/30014 , G06F9/30025 , G06F9/30036 , G06F9/30167 , G06F9/3877
摘要： A data processor includes both integer and floating point operation units and operates as a reduced instruction set computer (RISC). A modification of the normal load/store RISC operations includes within in its instruction set some instructions that permit floating point operations to be paired with load or store operations. These operations include: vector floating point add; vector multiply accumulate; vector floating point multiply; vector multiply subtract; vector reverse subtract; vector round floating point input; vector round integer input; and vector floating point subtract.
摘要翻译： 数据处理器包括整数和浮点运算单元，并作为精简指令集计算机（RISC）运行。 正常加载/存储RISC操作的修改包括在其指令集中的一些允许浮点运算与加载或存储操作配对的指令。 这些操作包括：向量浮点添加; 向量乘积 向量浮点乘法; 矢量乘法; 矢量反向减法; 向量圆浮点输入; 向量圆整数输入; 和向量浮点减法。
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68.发明授权Method for simulating views of a scene using expanded pixel data to reduce the amount of pixel data recalculations 失效用于使用扩展的像素数据模拟场景的视图以减少像素数据重新计算量的方法
公开(公告)号：US5646640A
公开(公告)日：1997-07-08
申请号：US382274
申请日：1995-01-31
申请人： Robert J. Gove
发明人： Robert J. Gove
摘要： A device (10) simulates a user's view (12) of a scene (16) on a display (24). A memory (36) stores region pixel data that represent a region (14) of the scene (16). A sensor (20) provides information that represents the direction and orientation of the user's gaze. A processor (32) determines the coordinates of the view (12) from the direction and orientation information, determines which of the region pixel data represent the view (12), and provides the determined view pixel data to the display (24).
摘要翻译： 设备（10）模拟用户在显示器（24）上的场景（16）的视图（12）。 存储器（36）存储表示场景（16）的区域（14）的区域像素数据。 传感器（20）提供表示用户目标的方向和方向的信息。 处理器（32）根据方向和方向信息确定视图（12）的坐标，确定区域像素数据中的哪一个表示视图（12），并将确定的视图像素数据提供给显示器（24）。
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69.发明授权Three input arithmetic logic unit with controllable shifter and mask generator 失效三输入算术逻辑单元，带可控制移位器和掩码发生器
公开(公告)号：US5634065A
公开(公告)日：1997-05-27
申请号：US475134
申请日：1995-06-07
申请人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Philip Moyse
发明人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Philip Moyse
摘要： A three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. The second input signal comes from a controllable barrel rotator (235). The rotate amount is a default rotate amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the barrel rotator (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the rotate amount. The output of the barrel rotator (235) may be stored independently of the arithmetic logic unit (230) result. The third input signal comes from a multiplexer (233) that selects between an instruction specified immediate field, data recalled from a data register or a mask input from a mask generator (239). One preferred form of the mask has a number of right justified 1's corresponding to a mask input signal. This mask input signal may be the default barrel rotate amount or a predetermined number of the least significant bits of a third input signal as selected by a multiplexer. A second preferred form of the mask is selected one of the left most 1, the right most 1, the left most bit change or the right most bit change of a predetermined set of the least significant bits of data recalled from a data register.
摘要翻译： 三输入算术逻辑单元（230），其生成由功能信号选择的三个输入的组合。 第二输入信号来自可控筒旋转器（235）。 旋转量是存储在特殊数据寄存器中的默认旋转量，从数据寄存器或零调用的预定数据位组。 恒定源（236）连接到筒旋转器（235）以提供“1”的多位数字信号。 这允许产生形式2N的第二输入信号，其中N是旋转量。 桶旋转器（235）的输出可以独立于算术逻辑单元（230）的结果存储。 第三输入信号来自多路复用器（233），其在指定的指令字段，从数据寄存器调用的数据或从掩码生成器输入的掩码（239）之间进行选择。 掩模的一个优选形式具有对应于掩模输入信号的许多右对齐1。 该掩模输入信号可以是由多路复用器选择的默认桶旋转量或第三输入信号的预定数量的最低有效位。 选择掩模的第二优选形式是从数据寄存器回调的数据的最低有效位的预定集合的最左1，最右1，最左位变化或最右位变化中的一个。
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公开(公告)号：US5608468A
公开(公告)日：1997-03-04
申请号：US482477
申请日：1995-06-07
CPC分类号： H04N7/0122 , H04N5/7458
摘要： A spatial light modulator with hexagonal elements or pixels. The elements include a reflective hexagonal surface supported by flexible hinges. The hinges are in turn supported by support posts away from a substrate. On the substrate are control or address electrodes which control the direction of deflection of the reflective surface by selective build up of electrostatic forces. The use of hexagonal pixels allow the posts and electrodes to be arrayed in horizontal lines, thereby allowing reset of horizontal lines of the pixels.
摘要翻译： 具有六边形元素或像素的空间光调制器。 元件包括由柔性铰链支撑的反射六边形表面。 铰链又由远离基底的支撑柱支撑。 在基板上是通过选择性地建立静电力来控制反射表面的偏转方向的控制或寻址电极。 使用六边形像素允许柱和电极以水平线排列，从而允许像素的水平线的复位。
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