公开(公告)号：US4380749A

公开(公告)日：1983-04-19

申请号：US220343

申请日：1980-12-29

申请人： Charles W. Eichelberger ,  Robert J. Wojnarowski

发明人： Charles W. Eichelberger ,  Robert J. Wojnarowski

IPC分类号： H01C7/10 ,  H01C13/00

CPC分类号： H01C7/10

摘要： A one-time electrically-activated switch is composed of a cured polymeric binder which contains a powdered conductive material in an amount sufficient to establish particle-to-particle contact throughout the binder and in which the material powder particles have a non-conductive oxide surface sufficient to resist the flow of electricity below a given threshold. When a sufficiently high voltage is applied to the switch, the break-down voltage of the oxide layer is exceeded and avalanche current is permitted to flow. As a result, the oxide layer on the conductive particles breaks down along the break-down path and forms an irreversible low-impedance connection.

摘要翻译： 一次性电激活开关由固化的聚合物粘合剂组成，其包含粉末状导电材料，其量足以在整个粘合剂中建立颗粒与颗粒的接触，并且其中材料粉末颗粒具有非导电氧化物表面 足以抵抗低于给定阈值的电流。 当对开关施加足够高的电压时，超过氧化物层的击穿电压，允许雪崩电流流动。 结果，导电粒子上的氧化物层沿断裂线分解，形成不可逆的低阻抗连接。

公开(公告)号：US4290052A

公开(公告)日：1981-09-15

申请号：US88287

申请日：1979-10-26

申请人： Charles W. Eichelberger ,  Robert J. Wojnarowski

发明人： Charles W. Eichelberger ,  Robert J. Wojnarowski

IPC分类号： G06F3/033 ,  G06F3/044 ,  G06K9/00 ,  H03K17/96 ,  H05K1/16 ,  H05K3/28 ,  G06F3/02 ,  H01G7/00

CPC分类号： G06F3/044 ,  G06K9/0002 ,  H03K17/9622 ,  H03K2017/9615 ,  H03K2217/96077 ,  H03K2217/960775 ,  H05K1/162 ,  H05K3/28

摘要： A capacitive touch entry structure utilizes an array of at least one capacitive touch sensor fabricated upon a double-sided printed circuit board adhesively mounted upon a surface of a transparent insulative substrate. The substrate has sufficient thickness to safely insulate user personnel, contacting the substrate surface furthest from an electrode of the capacitive touch sensor, from electrical potentials present adjacent to the panel surface upon which the capacitive touch sensor is fastened. Touch sensor circuitry and interconnections may be advantageously fabricated directly upon the pair of conductive planes, sandwiching an insulative layer therebetween, to form the printed circuit portion of the structure. A conductive guard may also be disposed adjacent to the substrate to shield at least the lead portions of the touch sensors from capacitive effects.

摘要翻译： 电容触摸输入结构利用在粘合地安装在透明绝缘基板的表面上的双面印刷电路板上制造的至少一个电容式触摸传感器的阵列。 基板具有足够的厚度，以安全地绝缘用户人员，使与电容式触摸传感器的电极最远的基板表面与电容触摸传感器紧固在其上的面板表面相邻的电位接触。 触摸传感器电路和互连可以有利地直接在一对导电平面上制造，在其间夹有绝缘层，以形成结构的印刷电路部分。 还可以将导电保护件设置成与衬底相邻以至少屏蔽触摸传感器的引线部分免受电容效应。

公开(公告)号：US08564119B2

公开(公告)日：2013-10-22

申请号：US12611405

申请日：2009-11-03

申请人： Charles W. Eichelberger ,  James E. Kohl

发明人： Charles W. Eichelberger ,  James E. Kohl

IPC分类号： H01L23/36

CPC分类号： H05K3/30 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/29 ,  H01L23/3128 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L24/82 ,  H01L24/96 ,  H01L25/0652 ,  H01L2221/68345 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2224/24137 ,  H01L2224/2518 ,  H01L2224/96 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/3511 ,  H05K1/0206 ,  H05K1/0218 ,  H05K1/185 ,  H05K3/4644 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/10371 ,  H05K2201/10674 ,  H05K2203/0733 ,  Y10T29/49121 ,  Y10T29/49124 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49155 ,  H01L2924/00

摘要： Circuit structures and methods of fabrication are provided for facilitating implementing a complete electronic system in a compact package. The circuit structure includes, in one embodiment, a chips-first multichip base layer with conductive structures extending therethrough. An interconnect layer is disposed over the front surface of the multichip layer and includes interconnect metallization electrically connected to contact pads of the chips and to conductive structures extending through the structural material. A redistribution layer, disposed over the back surface of the multichip layer, includes a redistribution metallization also electrically connected to conductive structures extending through the structural material. Input/output contacts are arrayed over the redistribution layer, including over the lower surfaces of at least some integrated circuit chips within the multichip layer, and are electrically connected through the redistribution metallization, conductive structures, and interconnect metallization to contact pads of the integrated circuit chips of the multichip layer.

摘要翻译： 提供了电路结构和制造方法，以便于以紧凑的封装实现完整的电子系统。 在一个实施例中，电路结构包括具有延伸穿过其中的导电结构的芯片 - 第一多芯片基底层。 互连层设置在多芯层的前表面上，并且包括电连接到芯片的接触焊盘和延伸穿过结构材料的导电结构的互连金属化。 设置在多芯层的后表面上的再分配层包括还电连接到延伸穿过结构材料的导电结构的再分布金属化。 输入/输出触点排列在再分配层上，包括在多芯层内的至少一些集成电路芯片的下表面上，并且通过再分布金属化，导电结构和互连金属化电连接到集成电路的接触焊盘 多芯片层的芯片。

公开(公告)号：US08324020B2

公开(公告)日：2012-12-04

申请号：US12611412

申请日：2009-11-03

申请人： Charles W. Eichelberger ,  James E. Kohl

发明人： Charles W. Eichelberger ,  James E. Kohl

IPC分类号： H01L21/00

CPC分类号： H05K3/30 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/29 ,  H01L23/3128 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L24/82 ,  H01L24/96 ,  H01L25/0652 ,  H01L2221/68345 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2224/24137 ,  H01L2224/2518 ,  H01L2224/96 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/3511 ,  H05K1/0206 ,  H05K1/0218 ,  H05K1/185 ,  H05K3/4644 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/10371 ,  H05K2201/10674 ,  H05K2203/0733 ,  Y10T29/49121 ,  Y10T29/49124 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49155 ,  H01L2924/00

摘要： Circuit structures and methods of fabrication are provided for facilitating implementing a complete electronic system in a compact package. The circuit structure includes, in one embodiment, a chips-first multichip base layer with conductive structures extending therethrough. An interconnect layer is disposed over the front surface of the multichip layer and includes interconnect metallization electrically connected to contact pads of the chips and to conductive structures extending through the structural material. A redistribution layer, disposed over the back surface of the multichip layer, includes a redistribution metallization also electrically connected to conductive structures extending through the structural material. Input/output contacts are arrayed over the redistribution layer, including over the lower surfaces of at least some integrated circuit chips within the multichip layer, and are electrically connected through the redistribution metallization, conductive structures, and interconnect metallization to contact pads of the integrated circuit chips of the multichip layer.

摘要翻译： 提供了电路结构和制造方法，以便于以紧凑的封装实现完整的电子系统。 在一个实施例中，电路结构包括具有延伸穿过其中的导电结构的芯片 - 第一多芯片基底层。 互连层设置在多芯层的前表面上，并且包括电连接到芯片的接触焊盘和延伸穿过结构材料的导电结构的互连金属化。 设置在多芯层的后表面上的再分配层包括还电连接到延伸穿过结构材料的导电结构的再分布金属化。 输入/输出触点排列在再分配层上，包括在多芯层内的至少一些集成电路芯片的下表面上，并且通过再分布金属化，导电结构和互连金属化电连接到集成电路的接触焊盘 多芯片层的芯片。

公开(公告)号：US07830000B2

公开(公告)日：2010-11-09

申请号：US12144717

申请日：2008-06-24

申请人： Charles W. Eichelberger ,  James E. Kohl

发明人： Charles W. Eichelberger ,  James E. Kohl

IPC分类号： H01L23/34

CPC分类号： H05K3/30 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/29 ,  H01L23/3128 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L24/82 ,  H01L24/96 ,  H01L25/0652 ,  H01L2221/68345 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2224/24137 ,  H01L2224/2518 ,  H01L2224/96 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/3511 ,  H05K1/0206 ,  H05K1/0218 ,  H05K1/185 ,  H05K3/4644 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/10371 ,  H05K2201/10674 ,  H05K2203/0733 ,  Y10T29/49121 ,  Y10T29/49124 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49155 ,  H01L2924/00

摘要： Circuit structures and methods of fabrication are provided for facilitating implementing a complete electronic system in a compact package. The circuit structure includes, in one embodiment, a chips-first multichip base layer with conductive structures extending therethrough. An interconnect layer is disposed over the front surface of the multichip layer and includes interconnect metallization electrically connected to contact pads of the chips and to conductive structures extending through the structural material. A redistribution layer, disposed over the back surface of the multichip layer, includes a redistribution metallization also electrically connected to conductive structures extending through the structural material. Input/output contacts are arrayed over the redistribution layer, including over the lower surfaces of at least some integrated circuit chips within the multichip layer, and are electrically connected through the redistribution metallization, conductive structures, and interconnect metallization to contact pads of the integrated circuit chips of the multichip layer.

摘要翻译： 提供了电路结构和制造方法，以便于以紧凑的封装实现完整的电子系统。 在一个实施例中，电路结构包括具有延伸穿过其中的导电结构的芯片 - 第一多芯片基底层。 互连层设置在多芯层的前表面上，并且包括电连接到芯片的接触焊盘和延伸穿过结构材料的导电结构的互连金属化。 设置在多芯层的后表面上的再分配层包括还电连接到延伸穿过结构材料的导电结构的再分布金属化。 输入/输出触点排列在再分配层上，包括在多芯层内的至少一些集成电路芯片的下表面上，并且通过再分布金属化，导电结构和互连金属化电连接到集成电路的接触焊盘 多芯片层的芯片。

公开(公告)号：US20080315391A1

公开(公告)日：2008-12-25

申请号：US12144840

申请日：2008-06-24

申请人： James E. Kohl ,  Charles W. Eichelberger

发明人： James E. Kohl ,  Charles W. Eichelberger

IPC分类号： H01L23/48 ,  H01L21/56

CPC分类号： H05K3/30 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/29 ,  H01L23/3128 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L24/82 ,  H01L24/96 ,  H01L25/0652 ,  H01L2221/68345 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2224/24137 ,  H01L2224/2518 ,  H01L2224/96 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/3511 ,  H05K1/0206 ,  H05K1/0218 ,  H05K1/185 ,  H05K3/4644 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/10371 ,  H05K2201/10674 ,  H05K2203/0733 ,  Y10T29/49121 ,  Y10T29/49124 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49155 ,  H01L2924/00

摘要： Electronic modules and methods of fabrication are provided implementing a first metallization level directly on a chips-first chip layer. The chips-first layer includes chips, each with a pad mask over an upper surface and openings to expose chip contact pads. Structural dielectric material surrounds and physically contacts the side surfaces of the chips, and has an upper surface which is parallel to an upper surface of the chips. A metallization layer is disposed over the front surface of the chips-first layer, residing at least partially on the pad masks of the chips, and extending over one or more edges of the chips. Together, the pad masks of the chips, and the structural dielectric material electrically isolate the metallization layer from the edges of the chips, and from one or more electrical structures of the chips in the chips-first layer.

摘要翻译： 提供电子模块和制造方法，其直接在芯片第一芯片层上实现第一金属化级别。 芯片第一层包括芯片，每个芯片在上表面上具有焊盘掩模和开口以暴露芯片接触焊盘。 结构介电材料围绕并物理接触芯片的侧表面，并具有平行于芯片上表面的上表面。 金属化层设置在芯片第一层的前表面上，至少部分地驻留在芯片的焊盘掩模上，并且在芯片的一个或多个边缘上延伸。 一起，芯片的焊盘掩模和结构介电材料将金属化层与芯片的边缘以及芯片第一层中的芯片的一个或多个电结构电隔离。

公开(公告)号：US5144747A

公开(公告)日：1992-09-08

申请号：US676938

申请日：1991-03-27

申请人： Charles W. Eichelberger

发明人： Charles W. Eichelberger

IPC分类号： H01L21/00

CPC分类号： H01L24/19 ,  H01L21/67121 ,  H01L21/6835 ,  H01L23/5389 ,  H01L2221/68359 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01056 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/351 ,  Y10S977/788 ,  Y10S977/90 ,  Y10S977/951 ,  Y10T29/49131 ,  Y10T29/49133 ,  Y10T29/49144 ,  Y10T29/53178

摘要： A multichip integrated circuit package comprises a substrate having a flat upper surface to which is affixed one or more integrated circuit chips having interconnection pads. A polymer encapsulant completely surrounds the integrated circuit chips. The encapsulant is provided with a plurality of via openings therein to accommodate a layer of interconnection metallization. The metallization serves to connect various chips and chip pads with the interconnection pads disposed on the chips. In specific embodiments, the module is constructed to be repairable, have high I/O capability with optimal heat removal, have optimized speed, be capable of incorporating an assortment of components of various thicknesses and function, and be hermetically sealed with a high I/O count. Specific processing methods for each of the various module features are described herein, along with additional structural enhancements.

摘要翻译： 多芯片集成电路封装包括具有平坦的上表面的基板，其上贴有一个或多个具有互连焊盘的集成电路芯片。 聚合物密封剂完全围绕集成电路芯片。 密封剂在其中设置有多个通孔以容纳互连金属化层。 金属化用于将各种芯片和芯片焊盘与布置在芯片上的互连焊盘连接。 在具体实施例中，该模块被构造为可修复的，具有高的I / O能力，具有最佳散热，具有优化的速度，能够结合各种厚度和功能的各种组件，并且可以用高I / O计数 这里描述了各种模块特征中的每一个的具体处理方法以及附加的结构增强。

公开(公告)号：US5111278A

公开(公告)日：1992-05-05

申请号：US676936

申请日：1991-03-27

申请人： Charles W. Eichelberger

发明人： Charles W. Eichelberger

IPC分类号： H01L25/00 ,  H01L23/473 ,  H01L23/538 ,  H01L25/065 ,  H05K1/18 ,  H05K3/46

CPC分类号： H05K1/185 ,  H01L23/473 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L25/0652 ,  H05K1/0272 ,  H01L2224/13025 ,  H01L2224/24137 ,  H01L2224/24225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01052 ,  H01L2924/01056 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/12033 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/10674 ,  H05K3/4623 ,  H05K3/4644

摘要： Multichip integrated circuit packages and methods of fabrication, along with systems for stacking such packages, are disclosed. In one embodiment, the multichip package has an array of contact pads on an upper surface thereof and an array of contact pads on a lower surface thereof. Connection means are provided for electrically coupling at least some of the contact pads on each package surface with selected ones of the contact pads on the other surface, or selected interconnection metallization which is disposed between integrated circuits located within the package. The contact pads of each surface array are preferably equal in number and vertically aligned such that multiple multichip packages may be readily stacked, with a conductive means disposed therebetween for electrically coupling the contact pads of one package to the pads of another package. In addition, various internal and external heat sink structures are provided which facilitate dissipation of heat in a multichip package or in a stack of multichip packages. Specific processing methods for each of the various multichip modules and stack systems disclosed are described herein.

摘要翻译： 公开了多芯片集成电路封装和制造方法以及用于堆叠这种封装的系统。 在一个实施例中，多芯片封装具有在其上表面上的接触焊盘阵列和其下表面上的接触焊盘阵列。 提供了连接装置，用于将每个封装表面上的至少一些接触焊盘与另一表面上的接触焊盘中的一个接触焊盘电耦合，或者设置在位于封装内的集成电路之间的选定的互连金属化。 每个表面阵列的接触垫优选地数量相等并且垂直对齐，使得可以容易地堆叠多个多芯片封装，其中设置有导电装置以将一个封装的接触焊盘电耦合到另一封装的焊盘。 此外，提供了各种内部和外部散热器结构，其有助于在多芯片封装或多芯片封装的堆叠中散热。 这里描述了所公开的各种多芯片模块和堆叠系统中的每一个的具体处理方法。

公开(公告)号：US5091893A

公开(公告)日：1992-02-25

申请号：US504750

申请日：1990-04-05

申请人： Lowell S. Smith ,  Charles W. Eichelberger ,  Robert J. Wojnarowksi ,  Wiliam P. Kornrumpf ,  Joseph E. Piel, Jr.

发明人： Lowell S. Smith ,  Charles W. Eichelberger ,  Robert J. Wojnarowksi ,  Wiliam P. Kornrumpf ,  Joseph E. Piel, Jr.

IPC分类号： B06B1/06

CPC分类号： B06B1/0629 ,  Y10T29/42

摘要： A piezoelectric ultrasonic array transducer has its individual elements connected to external electronics via a high density interconnect structure which facilitates signal connection and uniformity from array-to-array. The array fabrication process is preferably modified for use with a high density interconnect structure in order to obtain maximum transducer quality.

摘要翻译： 压电超声阵列换能器具有通过高密度互连结构连接到外部电子元件的单独元件，其有助于从阵列到阵列的信号连接和均匀性。 为了获得最大的换能器质量，阵列制造工艺优选地被修改为与高密度互连结构一起使用。

公开(公告)号：US4388566A

公开(公告)日：1983-06-14

申请号：US235191

申请日：1981-02-17

申请人： James F. Bedard ,  Charles W. Eichelberger ,  De-Yu Chen

发明人： James F. Bedard ,  Charles W. Eichelberger ,  De-Yu Chen

IPC分类号： H05B41/392 ,  G05F1/00

CPC分类号： H05B41/3921 ,  Y10S315/04

摘要： A passive control network for connection between a pair of load output level setting terminals, as on a ballast for a dimmable fluorescent lamp in a lighting system, to provide a required variable impedance, where the magnitude of the impedance establishes the load output level. The passive control network includes an isolation transformer for coupling a periodic waveform at the load input terminals to the variable impedance component, the magnitude of which impedance is reflected through the transformer to provide the load level-setting impedance.

摘要翻译： 用于连接一对负载输出电平设置端子的无源控制网络，如在照明系统中用于可调光荧光灯的镇流器，以提供所需的可变阻抗，其中阻抗的大小建立负载输出电平。 无源控制网络包括隔离变压器，用于将负载输入端子处的周期性波形耦合到可变阻抗分量，其阻抗的大小通过变压器反射以提供负载电平设置阻抗。