公开(公告)号：US20230178425A1

公开(公告)日：2023-06-08

申请号：US18151662

申请日：2023-01-09

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Roshan Jayakhar TIRUKKONDA ,  Bing ZHOU ,  Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Senaka KANAKAMEDALA ,  Adarsh RAJASHEKHAR

IPC: H01L21/768 ,  H01L21/306

CPC classification number: H01L21/76831 ,  H01L21/30608

Abstract: A method of forming a structure includes forming an alternating stack of first material layers and second material layers over a substrate, forming a first etch mask material layer, forming a first cladding liner, and forming a via opening through the alternating stack by performing an anisotropic etch process that employs a combination of at least the first cladding liner and the first etch mask material layer as a composite etch mask structure.

公开(公告)号：US20230018394A1

公开(公告)日：2023-01-19

申请号：US17378196

申请日：2021-07-16

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Raghuveer S. MAKALA ,  Senaka KANAKAMEDALA ,  Rahul SHARANGPANI ,  Ramy Nashed Bassely SAID

IPC: H01L27/1157 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/06

Abstract: A three-dimensional memory device includes a vertical repetition of multiple instances of a unit layer stack. The unit layer stack includes, in order, an airgap-containing insulating layer, a first interfacial dielectric capping layer, a metal layer, and a second interfacial dielectric capping layer. Memory stack structures extend through the vertical repetition. Each of the memory stack structures includes a vertical semiconductor channel and a vertical stack of memory elements located at levels of the metal layers.

公开(公告)号：US20220231048A1

公开(公告)日：2022-07-21

申请号：US17150561

申请日：2021-01-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Fei ZHOU ,  Adarsh RAJASHEKHAR

IPC: H01L27/11597 ,  H01L27/11587 ,  H01L27/1159

Abstract: A ferroelectric memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and containing a vertical stack of memory elements and a vertical semiconductor channel. Each memory element within the vertical stack of memory elements includes a crystalline ferroelectric memory material portion and an epitaxial template portion.

公开(公告)号：US20220208785A1

公开(公告)日：2022-06-30

申请号：US17136471

申请日：2020-12-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Monica TITUS ,  Senaka KANAKAMEDALA ,  Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Yao-Sheng LEE

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11519

Abstract: An alternating stack of first material layers and second material layers is formed over a substrate. A hard mask layer is formed over the alternating stack. Optionally, an additional hard mask layer can be formed over the hard mask layer. A photoresist layer is applied and patterned, and cavities are formed in the hard mask layer by performing a first anisotropic etch process that transfers a pattern of the openings in the photoresist layer through the hard mask layer. Via openings are formed through an upper portion of the alternating stack by performing a second anisotropic etch process. A cladding liner can be optionally formed on sidewalls of the cavities in the hard mask layer. The via openings can be vertically extend through all layers within the alternating stack by performing a third anisotropic etch process.

公开(公告)号：US20220208600A1

公开(公告)日：2022-06-30

申请号：US17508036

申请日：2021-10-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Roshan Jayakhar TIRUKKONDA ,  Senaka KANAKAMEDALA ,  Raghuveer S. MAKALA ,  Rahul SHARANGPANI ,  Monica TITUS ,  Adarsh RAJASHEKHAR

IPC: H01L21/768 ,  H01L21/306 ,  H01L21/308

Abstract: A source-level semiconductor layer and an alternating stack of first material layers and second material layers is formed above a substrate. A hard mask layer is formed over the alternating stack, and is subsequently patterned to provide a pattern of cavities therethrough. Via openings are formed through the alternating stack by performing an anisotropic etch process. A cladding liner is formed on sidewalls of the cavities in the hard mask layer and on a top surface of the hard mask layer. The via openings are vertically extended at least through the source-level semiconductor layer by performing a second anisotropic etch process employing a combination of the cladding liner and the hard mask layer as an etch mask.

公开(公告)号：US20210358952A1

公开(公告)日：2021-11-18

申请号：US16876816

申请日：2020-05-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Raghuveer S. Makala ,  Yanli ZHANG ,  Fei ZHOU ,  Rahul SHARANGPANI ,  Adarsh RAJASHEKHAR ,  Seung-Yeul YANG

IPC: H01L27/11597 ,  H01L27/11587 ,  H01L27/1159 ,  H01L23/522 ,  H01L23/528

Abstract: A memory opening or a line trench is formed through an alternating stack of insulating layers and sacrificial material layers. A memory opening fill structure or a memory stack assembly is formed, which includes a vertical stack of discrete intermediate metallic electrodes formed on sidewalls of the sacrificial material layers, a gate dielectric layer, and a vertical semiconductor channel. Backside recesses are formed by removing the sacrificial material layers selective to the insulating layers, and a combination of a ferroelectric dielectric layer and an electrically conductive layer within each of the backside recesses. The electrically conductive layer is laterally spaced from a respective one of the discrete intermediate metallic electrodes by the ferroelectric dielectric layer. Ferroelectric-metal-insulator memory elements are formed around the vertical semiconductor channel.

公开(公告)号：US20210202703A1

公开(公告)日：2021-07-01

申请号：US16728825

申请日：2019-12-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Adarsh RAJASHEKHAR ,  Fei ZHOU ,  Raghuveer S. MAKALA ,  Yanli ZHANG ,  Rahul SHARANGPANI

IPC: H01L29/417 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11597

Abstract: A three-dimensional memory device includes an alternating stack of source layers and drain layers located over a substrate, memory openings vertically extending through the alternating stack, vertical word lines located in each one of the memory openings and vertically extending through each of the source layers and the drain layers of the alternating stack, vertical stacks of discrete semiconductor channels located in each one of the memory openings and contacting horizontal surfaces of a respective vertically neighboring pair of a source layer of the source layers and a drain layer of the drain layers, and vertical stacks of discrete memory material portions located in each one of the memory openings and laterally surrounding a respective one of the vertical word lines. Each memory material portion is laterally spaced from a respective one of the semiconductor channels by a respective gate dielectric layer.

公开(公告)号：US20210074727A1

公开(公告)日：2021-03-11

申请号：US17081122

申请日：2020-10-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Bhagwati PRASAD ,  Rahul SHARANGPANI

IPC: H01L27/11597 ,  H01L27/11587 ,  H01L27/1159

Abstract: An antiferroelectric memory device includes at least one antiferroelectric memory cell. Each of the at least one antiferroelectric memory cell includes a first electrode, a second electrode and a stack containing an antiferroelectric layer and a doped semiconductor layer or a ferroelectric layer located between the first and the second electrodes.

公开(公告)号：US20210066348A1

公开(公告)日：2021-03-04

申请号：US17081147

申请日：2020-10-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Bhagwati PRASAD ,  Rahul SHARANGPANI

IPC: H01L27/11597 ,  H01L27/1159 ,  H01L29/51 ,  H01L21/28 ,  H01L21/02

Abstract: An antiferroelectric memory device includes at least one antiferroelectric memory cell. Each of the at least one antiferroelectric memory cell includes a first electrode, a second electrode and a stack containing an antiferroelectric layer and a doped semiconductor layer or a ferroelectric layer located between the first and the second electrodes.

公开(公告)号：US20180097009A1

公开(公告)日：2018-04-05

申请号：US15286063

申请日：2016-10-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yanli ZHANG ,  Johann ALSMEIER ,  Raghuveer S. MAKALA ,  Senaka KANAKAMEDALA ,  Rahul SHARANGPANI ,  James KAI

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/7926

Abstract: A layer stack including an alternating stack of insulating layers and sacrificial material layers is formed over a substrate. After formation of memory stack structures, backside trenches are formed through the layer stack. The sacrificial material layers are replaced with electrically conductive layers. Drain select level dielectric isolation structures are formed through drain select level of the stack after formation of the electrically conductive layers. The drain select level dielectric isolation structures laterally separate portions of conductive layers that are employed as drain select level gate electrodes for the memory stack structures.