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    NEGATIVE BIT LINE BIASING DURING QUICK PASS WRITE PROGRAMMING
    62.
    发明申请
    NEGATIVE BIT LINE BIASING DURING QUICK PASS WRITE PROGRAMMING 有权

    公开(公告)号：US20220284965A1

    公开(公告)日：2022-09-08

    申请号：US17192598

    申请日：2021-03-04

    Applicant: SanDisk Technologies LLC

    Inventor： Yu-Chung Lien ,  Huai-yuan Tseng ,  Swaroop Kaza ,  Tomer Eliash

    IPC: G11C16/10 ,  G11C16/26 ,  G11C16/24 ,  G11C16/30

    Abstract: A method of operating a memory system includes a first programming loop, which includes applying a first programming voltage to a control gate of a selected word line and applying a first bitline voltage to a bitline coupled to a first memory cell that is being programmed to a first data state and to a different bitline coupled to a second memory cell that is being programmed to a second data state. In a second programming loop, a second bitline voltage is applied to the bitline coupled to the first memory cell, and a third bitline voltage is applied to the bitline coupled to the second memory cell. The second bitline voltage is greater than the first bitline voltage to reduce a programming speed of the first bitline voltage to increase a programming speed of the second memory cell.

    DYNAMIC TIER SELECTION FOR PROGRAM VERIFY IN NONVOLATILE MEMORY
    64.
    发明申请
    DYNAMIC TIER SELECTION FOR PROGRAM VERIFY IN NONVOLATILE MEMORY 有权

    公开(公告)号：US20210407603A1

    公开(公告)日：2021-12-30

    申请号：US16915663

    申请日：2020-06-29

    Applicant: SanDisk Technologies LLC

    Inventor： Yu-Chung Lien ,  Dengtao Zhao ,  Huai-Yuan Tseng

    IPC: G11C16/34 ,  G11C16/10 ,  G11C16/30 ,  G11C11/56

    Abstract: An apparatus includes a memory controller configured to apply selected one or ones of the program verify voltage levels to a single tier of memory cells. A memory controller is configured to: program data into the plurality of memory cells; and perform a program verify operation across multiple voltage levels with a first voltage level of the program verify operation being applied to a single tier that represents all of the tiers in the memory group and a second voltage level of the program verify operation being applied to multiple tiers, wherein the first voltage level is less than the second voltage level. In embodiments, less than all of the tiers, e.g., two or four tiers, can be used in the program verify to represent all of the tires

    PEAK POWER REDUCTION MANAGEMENT IN NON-VOLATILE STORAGE BY DELAYING START TIMES OPERATIONS
    65.
    发明申请
    PEAK POWER REDUCTION MANAGEMENT IN NON-VOLATILE STORAGE BY DELAYING START TIMES OPERATIONS 有权

    公开(公告)号：US20210405920A1

    公开(公告)日：2021-12-30

    申请号：US16912381

    申请日：2020-06-25

    Applicant: SanDisk Technologies LLC

    Inventor： Yu-Chung Lien ,  Mark Murin ,  Hua-Ling Cynthia Hsu ,  Tomer Eliash ,  Huai-Yuan Tseng ,  Deepanshu Dutta

    IPC: G06F3/06 ,  G11C16/10 ,  G11C16/32 ,  H01L25/065

    Abstract: Power and/or current regulation in non-volatile memory systems is disclosed. Peak power/current usage may be reduced by staggering concurrent program operations in the different semiconductor dies. Each set of one or more semiconductor dies has an earliest permitted start time for its program operation, as well as a number of permitted backup start times. The permitted start times are unique for each set of one or more semiconductor dies. There may be a uniform gap or delay between each permitted start time. If a semiconductor die is busy with another memory operation at or after its earliest permitted start time, then the program operation is initiated or resumed at one of the permitted backup times. By having permitted backup times, the memory system need not poll each semiconductor die to determine whether the semiconductor die is ready/busy in order to determine when a die should start a program operation.

    Wordline voltage overdrive methods and systems
    67.
    发明授权
    Wordline voltage overdrive methods and systems 有权

    公开(公告)号：US11081197B2

    公开(公告)日：2021-08-03

    申请号：US17066663

    申请日：2020-10-09

    Applicant: SanDisk Technologies LLC

    Inventor： Xiang Yang ,  Yu-Chung Lien

    IPC: G11C16/04 ,  G11C16/34 ,  G11C16/08 ,  G11C16/26 ,  G11C16/24 ,  G11C11/56

    Abstract: A methodology and structure for performing an erase verify in non-volatile memory is described. Both the odd wordlines and the even wordlines are driven to a high voltage level. This can be done simultaneously. The simultaneous charging of both the odd wordlines and the even wordlines, even when the erase verify will occur on only one of the odd or even wordlines reduces RC delay in the charging of the wordlines. After the odd and even wordlines are charged, then one set of wordlines, either the odd or even wordlines, is dropped to the erase verify voltage. The erase sense operation is then performed.

    Source side precharge and boosting improvement for reverse order program
    68.
    发明授权
    Source side precharge and boosting improvement for reverse order program 有权

    公开(公告)号：US11081162B1

    公开(公告)日：2021-08-03

    申请号：US16798718

    申请日：2020-02-24

    Applicant: SanDisk Technologies LLC

    Inventor： Sarath Puthenthermadam ,  Yu-Chung Lien ,  Huai-Yuan Tseng

    IPC: G11C16/04 ,  G11C11/4074 ,  G11C11/4094 ,  G11C5/14 ,  G11C7/14 ,  G11C5/02 ,  G11C11/408

    Abstract: This disclosure relates to apparatuses and a method for retaining a bias in a NAND string channel during source-side precharge. The apparatuses include a memory array and a die controller configured to mitigate formation of a potential gradient in the channel of the memory array NAND strings during a program storage operation. To this end, a plurality of source-side select gates is activated, then each of the plurality of source side dummy word line select gates is activated. Next, a NAND string channel is biased by biasing the source line coupled to the NAND string by the plurality of source-side select gates. Finally, the plurality of source-side select gates and the plurality of source side dummy word line select gates are discharged such that the channel maintains an electrical path to the source line.

    Peak and average current reduction for open block condition
    69.
    发明授权
    Peak and average current reduction for open block condition 有权

    公开(公告)号：US10902925B1

    公开(公告)日：2021-01-26

    申请号：US16688587

    申请日：2019-11-19

    Applicant: SanDisk Technologies LLC

    Inventor： Yu-Chung Lien ,  Michael Huai-Yuan Tseng ,  Deepanshu Dutta

    IPC: G11C16/04 ,  G11C16/26 ,  G11C16/34 ,  H01L27/11556 ,  H01L27/11582 ,  G11C16/08

    Abstract: A memory apparatus and method of operation is provided. The apparatus includes a block of memory cells arranged in strings and connected to word lines overlying one another in a stack. The apparatus includes a control circuit configured to determine whether the memory cells of the block are all programmed. The control circuit determines a boundary word line splitting the word lines into first and second word line sets connected to the memory cells that are respectively programmed and not programmed in response to determining the memory cells of the block are not all programmed. The control circuit applies a delta adjusted read voltage being a default read pass voltage minus a delta voltage to a subset of the second word line set separated from the boundary word line in the stack by at least an offset number of the word lines while reading a first group of memory cells.

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