公开(公告)号：US20140175435A1

公开(公告)日：2014-06-26

申请号：US14137476

申请日：2013-12-20

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei Yamazaki ,  Hideomi Suzawa ,  Tetsuhiro Tanaka ,  Hirokazu Watanabe ,  Yuhei Sato ,  Yasumasa Yamane ,  Daisuke Matsubayashi

IPC: H01L29/786

CPC classification number: H01L29/78618 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device having a reduced amount of oxygen vacancy in a channel formation region of an oxide semiconductor is provided. Further, a semiconductor device which includes an oxide semiconductor and has improved electric characteristics is provided. Furthermore, a methods for manufacturing the semiconductor device is provided. An oxide semiconductor film is formed; a conductive film is formed over the oxide semiconductor film at the same time as forming a low-resistance region between the oxide semiconductor film and the conductive film; the conductive film is processed to form a source electrode and a drain electrode; and oxygen is added to the low-resistance region between the source electrode and the drain electrode, so that a channel formation region having a higher resistance than the low-resistance region is formed and a first low-resistance region and a second low-resistance region between which the channel formation region is positioned are formed.

Abstract translation: 提供了在氧化物半导体的沟道形成区域中具有减少的氧空位量的半导体器件。 此外，提供了包括氧化物半导体并具有改善的电特性的半导体器件。 此外，提供了制造半导体器件的方法。 形成氧化物半导体膜; 在氧化物半导体膜和导电膜之间形成低电阻区域的同时，在氧化物半导体膜上形成导电膜; 处理导电膜以形成源电极和漏电极; 并且在源电极和漏极之间的低电阻区域添加氧，使得形成具有比低电阻区域更高的电阻的沟道形成区域，并且形成第一低电阻区域和第二低电阻 形成沟道形成区域所在的区域。

公开(公告)号：US12237424B2

公开(公告)日：2025-02-25

申请号：US18524033

申请日：2023-11-30

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei Yamazaki ,  Hideomi Suzawa

IPC: H01L29/12 ,  H01L29/04 ,  H01L29/49 ,  H01L29/51 ,  H01L29/786

Abstract: A transistor that is to be provided has such a structure that a source electrode layer and a drain electrode layer between which a channel formation region is sandwiched has regions projecting in a channel length direction at lower end portions, and an insulating layer is provided, in addition to a gate insulating layer, between the source and drain electrode layers and a gate electrode layer. In the transistor, the width of the source and drain electrode layers is smaller than that of an oxide semiconductor layer in the channel width direction, so that an area where the gate electrode layer overlaps with the source and drain electrode layers can be made small. Further, the source and drain electrode layers have regions projecting in the channel length direction at lower end portions.

公开(公告)号：US11770939B2

公开(公告)日：2023-09-26

申请号：US17513982

申请日：2021-10-29

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuta Endo ,  Hideomi Suzawa

IPC: H01L27/105 ,  H01L23/52 ,  H01L29/24 ,  H10B99/00 ,  H01L23/528 ,  H01L27/02 ,  H01L29/66 ,  H01L29/786

CPC classification number: H10B99/00 ,  H01L23/528 ,  H01L27/0207 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/7869

Abstract: A semiconductor device that can be highly integrated is provided. The semiconductor device includes a first transistor, a second transistor, and an electrode. The first transistor and the second transistor include an oxide, a gate insulator over the oxide, and a gate. The electrode is connected to one of a source and a drain of the first transistor and one of a source and a drain of the second transistor. The channel length of the first transistor is longer than the short side of the first conductor. The channel length of the second transistor is longer than the short side of the second conductor.

公开(公告)号：US11049974B2

公开(公告)日：2021-06-29

申请号：US16833918

申请日：2020-03-30

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Hideomi Suzawa ,  Tetsuhiro Tanaka ,  Hirokazu Watanabe ,  Yuhei Sato ,  Yasumasa Yamane ,  Daisuke Matsubayashi

IPC: H01L29/786 ,  H01L29/45 ,  H01L29/66

Abstract: A semiconductor device having a reduced amount of oxygen vacancy in a channel formation region of an oxide semiconductor is provided. Further, a semiconductor device which includes an oxide semiconductor and has improved electric characteristics is provided. Furthermore, a methods for manufacturing the semiconductor device is provided. An oxide semiconductor film is formed; a conductive film is formed over the oxide semiconductor film at the same time as forming a low-resistance region between the oxide semiconductor film and the conductive film; the conductive film is processed to form a source electrode and a drain electrode; and oxygen is added to the low-resistance region between the source electrode and the drain electrode, so that a channel formation region having a higher resistance than the low-resistance region is formed and a first low-resistance region and a second low-resistance region between which the channel formation region is positioned are formed.

公开(公告)号：US10923580B2

公开(公告)日：2021-02-16

申请号：US16671612

申请日：2019-11-01

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Hideomi Suzawa ,  Shinya Sasagawa ,  Motomu Kurata ,  Masashi Tsubuku

IPC: H01L29/66 ,  H01L29/786 ,  H01L21/02 ,  H01L27/12 ,  H01L27/146

Abstract: The on-state characteristics of a transistor are improved and thus, a semiconductor device capable of high-speed response and high-speed operation is provided. A highly reliable semiconductor device showing stable electric characteristics is made. The semiconductor device includes a transistor including a first oxide layer; an oxide semiconductor layer over the first oxide layer; a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer; a second oxide layer over the oxide semiconductor layer; a gate insulating layer over the second oxide layer; and a gate electrode layer over the gate insulating layer. An end portion of the second oxide layer and an end portion of the gate insulating layer overlap with the source electrode layer and the drain electrode layer.

公开(公告)号：US10720532B2

公开(公告)日：2020-07-21

申请号：US16558601

申请日：2019-09-03

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Masayuki Sakakura ,  Hideomi Suzawa

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/24 ,  H01L29/04 ,  H01L27/146 ,  H01L27/105 ,  H01L27/12 ,  H01L29/78

Abstract: A semiconductor device having a structure which can prevent a decrease in electrical characteristics due to miniaturization is provided. The semiconductor device includes, over an insulating surface, a stack in which a first oxide semiconductor layer and a second oxide semiconductor layer are sequentially formed, and a third oxide semiconductor layer covering part of a surface of the stack. The third oxide semiconductor layer includes a first layer in contact with the stack and a second layer over the first layer. The first layer includes a microcrystalline layer, and the second layer includes a crystalline layer in which c-axes are aligned in a direction perpendicular to a surface of the first layer.

公开(公告)号：US10403646B2

公开(公告)日：2019-09-03

申请号：US15041502

申请日：2016-02-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hideomi Suzawa ,  Yuta Endo ,  Kazuya Hanaoka

IPC: H01L27/12 ,  H01L29/786 ,  H01L21/475 ,  H01L21/4757

Abstract: A semiconductor device with reduced parasitic capacitance is provided. The semiconductor device includes a first insulating layer; a first oxide layer over the first insulating layer; a semiconductor layer over the first oxide layer; a source electrode layer and a drain electrode layer over the semiconductor layer; a second insulating layer over the first insulating layer; a third insulating layer over the second insulating layer, the source electrode layer, and the drain electrode layer; a second oxide layer over the semiconductor layer; a gate insulating layer over the second oxide layer; a gate electrode layer over the gate insulating layer; and a fourth insulating layer over the third insulating layer, the second oxide layer, the gate insulating layer, and the gate electrode layer.

公开(公告)号：US10256348B2

公开(公告)日：2019-04-09

申请号：US15903097

申请日：2018-02-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuta Endo ,  Hideomi Suzawa ,  Kazuya Hanaoka ,  Shinya Sasagawa ,  Satoru Okamoto

IPC: H01L29/40 ,  H01L29/786 ,  H01L27/12 ,  H01L27/146 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66

Abstract: A semiconductor device in which parasitic capacitance is reduced is provided. A first oxide insulating layer and a first oxide semiconductor layer are sequentially formed over a first insulating layer. A first conductive layer is formed over the first oxide semiconductor layer and etched to form a second conductive layer. The first oxide insulating layer and the first oxide semiconductor layer are etched with the second conductive layer as a mask to form a second oxide insulating layer and a second oxide semiconductor layer. A planarized insulating layer is formed over the first insulating layer and the second conductive layer. A second insulating layer, a source electrode layer, and a drain electrode layer are formed by etching the planarized insulating layer and the second conductive layer. A third oxide insulating layer, a gate insulating layer, and a gate electrode layer are formed over the second oxide semiconductor layer.

公开(公告)号：US10224433B2

公开(公告)日：2019-03-05

申请号：US15467288

申请日：2017-03-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuji Egi ,  Hideomi Suzawa ,  Shinya Sasagawa

IPC: H01L21/02 ,  H01L21/44 ,  H01L27/12 ,  H01L29/04 ,  H01L29/06 ,  H01L29/66 ,  H01L21/465 ,  H01L27/146 ,  H01L29/786 ,  H01L21/4757 ,  H01L21/4763

Abstract: In a semiconductor device including a transistor in which an oxide semiconductor layer, a gate insulating layer, and a gate electrode layer on side surfaces of which sidewall insulating layers are provided are stacked in this order, a source electrode layer and a drain electrode layer are provided in contact with the oxide semiconductor layer and the sidewall insulating layers. In a process for manufacturing the semiconductor device, a conductive layer and an interlayer insulating layer are stacked to cover the oxide semiconductor layer, the sidewall insulating layers, and the gate electrode layer. Then, parts of the interlayer insulating layer and the conductive layer over the gate electrode layer are removed by a chemical mechanical polishing method, so that a source electrode layer and a drain electrode layer are formed. Before formation of the gate insulating layer, cleaning treatment is performed on the oxide semiconductor layer.

公开(公告)号：US10199508B2

公开(公告)日：2019-02-05

申请号：US15704093

申请日：2017-09-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Yoshinobu Asami ,  Yutaka Okazaki ,  Motomu Kurata ,  Katsuaki Tochibayashi ,  Shinya Sasagawa ,  Kensuke Yoshizumi ,  Hideomi Suzawa

IPC: H01L29/49 ,  H01L29/786 ,  H01L29/66 ,  H01L21/4757 ,  H01L21/47 ,  H01L21/477 ,  H01L33/00 ,  H01L27/12

Abstract: A miniaturized transistor, a transistor with low parasitic capacitance, a transistor with high frequency characteristics, or a semiconductor device including the transistor is provided. The semiconductor device includes a first insulator, an oxide semiconductor over the first insulator, a first conductor and a second conductor that are in contact with the oxide semiconductor, a second insulator that is over the first and second conductors and has an opening reaching the oxide semiconductor, a third insulator over the oxide semiconductor and the second insulator, and a fourth conductor over the third insulator. The first conductor includes a first region and a second region. The second conductor includes a third region and a fourth region. The second region faces the third region with the first conductor and the first insulator interposed therebetween. The second region is thinner than the first region. The third region is thinner than the fourth region.