公开(公告)号：US10916513B2

公开(公告)日：2021-02-09

申请号：US16453475

申请日：2019-06-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Harsono S. Simka ,  Ganesh Hegde ,  Joon Goo Hong ,  Rwik Sengupta ,  Mark S. Rodder

IPC: H01L23/00 ,  H01L23/522 ,  H01L27/02 ,  H04L9/32 ,  H01L23/532 ,  G09C1/00

Abstract: A hardware-embedded security system is described. The system includes connective components, circuit elements and an insulator. The connective components include a variable conductivity layer that is conductive for a first stoichiometry and insulating for a second stoichiometry. A first portion of the circuit elements are connected to a first portion of the connective components and are active. A the second portion of the circuit elements are connected to a second portion of the connective components and are inactive. The insulator is adjacent to at least a portion of each of the connective components. The first stoichiometry is indistinguishable from the second stoichiometry via optical imaging and electron imaging of a portion of the insulator and the variable conductivity layer.

公开(公告)号：US10886224B2

公开(公告)日：2021-01-05

申请号：US16561340

申请日：2019-09-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Vassilios Gerousis ,  Rwik Sengupta ,  Joon Goo Hong ,  Kevin Michael Traynor

IPC: H01L23/528 ,  H01L23/522

Abstract: A tap cell configured to enable electrical connection from a buried power rail of an integrated circuit to a power distribution network includes. The tap cell includes a buried power rail layer including VDD and VSS power supply lines, insulating layers and metal layers alternately arranged on the buried power rail layer, a first power supply interconnect in metal layer M1 or higher electrically coupled to the VDD power supply line, and a second power supply interconnect in metal layer M1 or higher electrically connected to the VSS power supply line. The first power supply interconnect and the second power supply interconnect are configured to be electrically connected to the power distribution network, and the VDD and VSS power supply lines are configured to supply power from the power distribution network to the buried power rail of the integrated circuit. The tap cell is free of any active semiconductor devices.

公开(公告)号：US10861950B2

公开(公告)日：2020-12-08

申请号：US16121427

申请日：2018-09-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Rwik Sengupta ,  Mark Rodder ,  Joon Goo Hong ,  Titash Rakshit

IPC: H01L27/088 ,  H01L29/417 ,  H01L29/78 ,  H01L27/02 ,  H01L21/8234 ,  H01L27/118

Abstract: A field effect transistor including a source region, a drain region, a channel region extending between the source region and the drain region, a gate on the channel region, a gate contact on the gate at an active region of the gate, a source contact on the source region, a drain contact on the drain region, and recesses in the source and drain contacts substantially aligned with the gate contact. Upper surfaces of the recesses in the source and drain contacts are spaced below an upper surface of the gate by a depth.

公开(公告)号：US10825723B2

公开(公告)日：2020-11-03

申请号：US16283341

申请日：2019-02-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joon Goo Hong ,  Harsono Simka ,  Mark Stephen Rodder

IPC: H01L23/49 ,  H01L21/768 ,  H01L21/02 ,  H01L23/522 ,  H01L23/528

Abstract: In a method of making a semiconductor device, the method includes: forming a first conductive layer over a substrate; forming an insulating layer on the first conductive layer; forming a via through the insulating layer to expose the first conductive layer; forming a self-assembled monolayer (SAM) over a bottom of the via; forming a barrier layer at a sidewall of the via; removing the SAM over the bottom of the via; and forming a second conductive layer over the barrier layer and the bottom of the via such that the first conductive layer is electrically connected to the second conductive layer without the barrier layer between the first conductive layer and the second conductive layer at the bottom of the via.

公开(公告)号：US20190148410A1

公开(公告)日：2019-05-16

申请号：US15880156

申请日：2018-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joon Goo Hong ,  Kang Ill Seo ,  Borna J. Obradovic

IPC: H01L27/12 ,  H01L21/027 ,  H01L21/02 ,  H01L21/477 ,  H01L27/088

Abstract: A method for providing a semiconductor device is described. The method provides a plurality of fins. A first portion of each of the plurality of fins is covered by a mask. A second portion of each of the plurality of fins is exposed by the mask. The method also performs an anneal in a volume-increasing ambient, such as hydrogen, at anneal temperature(s) above one hundred degrees Celsius and not more than six hundred degrees Celsius. The second portion of each of the fins is exposed during the anneal such that the second portion of each of the fins undergoes a volume expansion.

公开(公告)号：US10205025B2

公开(公告)日：2019-02-12

申请号：US15276779

申请日：2016-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jorge A. Kittl ,  Joon Goo Hong ,  Dharmendar Reddy Palle ,  Mark S. Rodder

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66

Abstract: Methods to achieve strained channel finFET devices and resulting finFET devices are presented. In an embodiment, a method for processing a field effect transistor (FET) device may include forming a fin structure comprising a fin channel on a substrate. The method may also include forming a sacrificial epitaxial layer on a side of the fin structure. Additionally, the method may include forming a deep recess in a region that includes at least a portion of the fin structure, wherein the fin structure and sacrificial layer relax to form a strain on the fin channel. The method may also include depositing source/drain (SD) material in the deep recess to preserve the strain on the fin channel.

公开(公告)号：US20190012593A1

公开(公告)日：2019-01-10

申请号：US15806259

申请日：2017-11-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna J. Obradovic ,  Titash Rakshit ,  Rwik Sengupta ,  Joon Goo Hong ,  Ryan M. Hatcher ,  Jorge A. Kittl ,  Mark S. Rodder

IPC: G06N3/063 ,  H01L29/78 ,  H01L29/423

Abstract: A neuromorphic multi-bit digital weight cell configured to store a series of potential weights for a neuron in an artificial neural network. The neuromorphic multi-bit digital weight cell includes a parallel cell including a series of passive resistors in parallel and a series of gating transistors. Each gating transistor of the series of gating transistors is in series with one passive resistor of the series of passive resistors. The neuromorphic cell also includes a series of programming input lines connected to the series of gating transistors, an input terminal connected to the parallel cell, and an output terminal connected to the parallel cell.

公开(公告)号：US10026652B2

公开(公告)日：2018-07-17

申请号：US15343157

申请日：2016-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wei-E Wang ,  Mark S. Rodder ,  Borna J. Obradovic ,  Joon Goo Hong

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28

Abstract: Multi-Vt horizontal nanosheet devices and a method of making the same. In one embodiment, an integrated circuit includes a plurality of horizontal nanosheet devices (hNS devices) on a top surface of a substrate, the plurality of hNS devices including a first hNS device and a second hNS device spaced apart from each other horizontally. Each of the hNS devices includes a first and a second horizontal nanosheets spaced apart vertically; and a gate stack between the first and second horizontal nanosheets, the gate stack including a work function metal (WFM) layer. A thickness of the first and second horizontal nanosheets of the first hNS device is different from a thickness of the first and second horizontal nanosheets of the second hNS device, and a thickness of the WFM layer of the first hNS device is different from a thickness of the WFM layer of the second hNS device.

公开(公告)号：US20180076199A1

公开(公告)日：2018-03-15

申请号：US15348916

申请日：2016-11-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wei-E Wang ,  Joon Goo Hong

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/02 ,  H01L21/321 ,  H01L29/04

Abstract: A complimentary metal-oxide-semiconductor (CMOS) circuit including: a substrate; and a plurality of field-effect transistors on the substrate. Each of the field-effect transistors includes: a plurality of contacts; a source connected to one of the contacts; a drain connected to another one of the contacts; a gate; and a spacer between the gate and the contacts. The spacer of one of the field-effect transistors has a larger airgap than the spacer of another one of the field-effect transistors.

公开(公告)号：US09899529B2

公开(公告)日：2018-02-20

申请号：US15195886

申请日：2016-06-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joon Goo Hong ,  Borna Obradovic ,  Mark Rodder

IPC: H01L21/22 ,  H01L29/786 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L21/225

CPC classification number: H01L29/78642 ,  H01L21/2256 ,  H01L29/0676 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/78618 ,  H01L29/78654 ,  H01L29/78684 ,  H01L29/78696

Abstract: A method for making a self-aligned vertical nanosheet field effect transistor. A vertical trench is etched in a layered structure including a plurality of layers, using reactive ion etching, and filled, using an epitaxial process, with a vertical semiconductor nanosheet. A sacrificial layer from among the plurality of layers is etched out and replaced with a conductive (e.g., metal) gate layer coated with a high-dielectric-constant dielectric material. Two other layers from among the plurality of layers, one above and one below the gate layer, are doped, and act as dopant donors for a diffusion process that forms two PN junctions in the vertical semiconductor nanosheet.