公开(公告)号：US20120122283A1

公开(公告)日：2012-05-17

申请号：US13240560

申请日：2011-09-22

申请人： Jong-Won LEE ,  Jae-Seok Kim ,  Bo-Un Yoon

发明人： Jong-Won LEE ,  Jae-Seok Kim ,  Bo-Un Yoon

IPC分类号： H01L21/336 ,  H01L21/28

CPC分类号： H01L21/823842 ,  H01L21/823437 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/7835

摘要： A method includes forming a plurality of dummy gate structures on a substrate, each dummy gate structure including a dummy gate electrode and a dummy gate mask, forming a first insulation layer on the substrate and the dummy gate structures to fill a first space between the dummy gate structures, planarizing upper portions of the first insulation layer and the dummy gate structures, removing the remaining first insulation layer to expose a portion of the substrate, forming an etch stop layer on the remaining dummy gate structures and the exposed portion of the substrate, forming a second insulation layer on the etch stop layer to fill a second space between the dummy gate structures, planarizing upper portions of the second insulation layer and the etch stop layer to expose the dummy gate electrodes, removing the exposed dummy gate electrodes to form trenches, and forming metal gate electrodes in the trenches.

摘要翻译： 一种方法包括在衬底上形成多个虚拟栅极结构，每个虚拟栅极结构包括伪栅极电极和伪栅极掩模，在衬底上形成第一绝缘层和虚拟栅极结构以填充虚拟栅极结构之间的第一空间 栅极结构，平坦化第一绝缘层和伪栅极结构的上部，去除剩余的第一绝缘层以暴露衬底的一部分，在剩余的虚设栅极结构和衬底的暴露部分上形成蚀刻停止层， 在所述蚀刻停止层上形成第二绝缘层以填充所述虚拟栅极结构之间的第二空间，平坦化所述第二绝缘层的上部和所述蚀刻停止层以暴露所述伪栅电极，去除所述暴露的伪栅电极以形成沟槽 并且在沟槽中形成金属栅电极。

公开(公告)号：US20120064680A1

公开(公告)日：2012-03-15

申请号：US13228867

申请日：2011-09-09

申请人： Jung-Min Oh ,  Bo-Un Yoon ,  Gyu-Wan Choi ,  Kun-Tack Lee ,  Dae-Hyuk Kang ,  Im-Soo Park ,  Dong-Seok Lee ,  Young-Hoo Kim

发明人： Jung-Min Oh ,  Bo-Un Yoon ,  Gyu-Wan Choi ,  Kun-Tack Lee ,  Dae-Hyuk Kang ,  Im-Soo Park ,  Dong-Seok Lee ,  Young-Hoo Kim

IPC分类号： H01L21/336 ,  H01G13/06

CPC分类号： H01G13/06

摘要： A method of forming a capacitor structure and manufacturing a semiconductor device, the method of forming a capacitor structure including sequentially forming a first mold layer, a supporting layer, a second mold layer, an anti-bowing layer, and a third mold layer on a substrate having a conductive region thereon; partially removing the third mold layer, the anti-bowing layer, the second mold layer, the supporting layer, and the first mold layer to form a first opening exposing the conductive region; forming a lower electrode on a sidewall and bottom of the first opening, the lower electrode being electrically connected to the conductive region; further removing the third mold layer, the anti-bowing layer, and the second mold layer; partially removing the supporting layer to form a supporting layer pattern; removing the first mold layer; and sequentially forming a dielectric layer and upper electrode on the lower electrode and the supporting layer pattern.

摘要翻译： 一种形成电容器结构并制造半导体器件的方法，形成电容器结构的方法包括：依次形成第一模具层，支撑层，第二模具层，抗弯曲层和第三模具层 衬底，其上具有导电区域; 部分地去除第三模具层，抗弯曲层，第二模具层，支撑层和第一模具层，以形成暴露导电区域的第一开口; 在所述第一开口的侧壁和底部形成下电极，所述下电极电连接到所述导电区域; 进一步去除第三模具层，抗弯曲层和第二模具层; 部分地去除支撑层以形成支撑层图案; 去除第一模具层; 并且在下电极和支撑层图案上依次形成电介质层和上电极。

公开(公告)号：US08124526B2

公开(公告)日：2012-02-28

申请号：US12503440

申请日：2009-07-15

申请人： Suk-Hun Choi ,  Jong-Won Lee ,  Chang-Ki Hong ,  Bo-Un Yoon

发明人： Suk-Hun Choi ,  Jong-Won Lee ,  Chang-Ki Hong ,  Bo-Un Yoon

IPC分类号： H01L21/4763

CPC分类号： H01L27/11507 ,  H01L21/3105 ,  H01L21/31053 ,  H01L28/55

摘要： In methods of forming a thin ferroelectric layer and methods of manufacturing a semiconductor device, a preliminary ferroelectric layer is formed on a substrate by depositing a metal oxide including lead, zirconium and titanium. The surface of the preliminary ferroelectric layer is polished using a slurry composition including an acrylic acid polymer, abrasive particles, and water to form a thin ferroelectric layer on the substrate. The slurry composition may reduce a polishing rate of the preliminary ferroelectric layer such that removal of a bulk portion of the preliminary ferroelectric layer may be suppressed and the surface roughness of the preliminary ferroelectric layer may be improved.

摘要翻译： 在形成薄铁电体层的方法和制造半导体器件的方法中，通过沉积包括铅，锆和钛的金属氧化物，在衬底上形成初步铁电层。 使用包括丙烯酸聚合物，磨料颗粒和水的浆料组合物对预制铁电层的表面进行抛光，以在基材上形成薄铁电层。 浆料组合物可以降低预备铁电体层的抛光速率，从而可以抑制初级铁电层的体积部分的去除，并且可以提高预铁电层的表面粗糙度。

公开(公告)号：US20110201203A1

公开(公告)日：2011-08-18

申请号：US13025410

申请日：2011-02-11

申请人： Hyo-San Lee ,  Bo-Un Yoon ,  Kun-Tack Lee ,  Dae-Hyuk Kang ,  Seong-Ho Moon ,  So-Ra Han

发明人： Hyo-San Lee ,  Bo-Un Yoon ,  Kun-Tack Lee ,  Dae-Hyuk Kang ,  Seong-Ho Moon ,  So-Ra Han

IPC分类号： H01L21/311

CPC分类号： H01L21/31111 ,  H01L21/32134 ,  H01L21/76802 ,  H01L27/10852 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/11578 ,  H01L27/11582 ,  H01L28/91 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/66833 ,  H01L29/7926

摘要： In a method of forming a hole, an insulation layer is formed on a substrate, and a preliminary hole exposing the substrate is formed through the insulation layer. A photosensitive layer pattern including an organic polymer is then formed on the substrate to fill the preliminary hole. An etching gas including hydrogen fluoride (HF) or fluorine (F2) is then provided onto the photosensitive layer pattern to etch the insulation layer so that width of the preliminary hole is increased.

摘要翻译： 在形成孔的方法中，在基板上形成绝缘层，通过绝缘层形成露出基板的预备孔。 然后在基板上形成包含有机聚合物的感光层图案以填充预备孔。 然后将包含氟化氢（HF）或氟（F2）的蚀刻气体提供到感光层图案上以蚀刻绝缘层，使得预备孔的宽度增加。

公开(公告)号：US20110159660A1

公开(公告)日：2011-06-30

申请号：US12906184

申请日：2010-10-18

申请人： Dae-Hyuk Kang ,  Bo-Un Yoon ,  Kun-Tack Lee ,  Woo-Gwan Shim ,  Ji-Hoon Cha ,  Im-Soo Park ,  Hyo-San Lee ,  Young-Hoo Kim ,  Jung-Min Oh

发明人： Dae-Hyuk Kang ,  Bo-Un Yoon ,  Kun-Tack Lee ,  Woo-Gwan Shim ,  Ji-Hoon Cha ,  Im-Soo Park ,  Hyo-San Lee ,  Young-Hoo Kim ,  Jung-Min Oh

IPC分类号： H01L21/02 ,  H01G13/00

CPC分类号： H01L28/91 ,  H01L27/10817 ,  H01L27/10852 ,  H01L28/87

摘要： In a method of forming a capacitor, a first mold layer pattern including a first insulating material may be formed on a substrate. The first mold layer pattern may have a trench. A supporting layer including a second insulating material may be formed in the trench. The second insulating material may have an etching selectivity with respect to the first insulating material. A second mold layer may be formed on the first mold layer pattern and the supporting layer pattern. A lower electrode may be formed through the second mold layer and the first mold layer pattern. The lower electrode may make contact with a sidewall of the supporting layer pattern. The first mold layer pattern and the second mold layer may be removed. A dielectric layer and an upper electrode may be formed on the lower electrode and the supporting layer pattern.

摘要翻译： 在形成电容器的方法中，可以在基板上形成包括第一绝缘材料的第一模层图案。 第一模层图案可以具有沟槽。 可以在沟槽中形成包括第二绝缘材料的支撑层。 第二绝缘材料可以具有相对于第一绝缘材料的蚀刻选择性。 可以在第一模层图案和支撑层图案上形成第二模层。 可以通过第二模具层和第一模具层图案形成下部电极。 下电极可以与支撑层图案的侧壁接触。 可以去除第一模层图案和第二模层。 电介质层和上电极可以形成在下电极和支撑层图案上。

公开(公告)号：US07678625B2

公开(公告)日：2010-03-16

申请号：US11962742

申请日：2007-12-21

申请人： Jong-Heun Lim ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Seong-Kyu Yun ,  Suk-Hun Choi ,  Sang-Yeob Han

发明人： Jong-Heun Lim ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Seong-Kyu Yun ,  Suk-Hun Choi ,  Sang-Yeob Han

IPC分类号： H01L21/84

CPC分类号： H01L21/02675 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L29/78

摘要： A method of fabricating a semiconductor device including a channel layer includes forming a single crystalline semiconductor layer on a semiconductor substrate. The single crystalline semiconductor layer includes a protrusion extending from a surface thereof. A first polishing process is performed on the single crystalline semiconductor layer to remove a portion of the protrusion such that the single crystalline semiconductor layer includes a remaining portion of the protrusion. A second polishing process different from the first polishing process is performed to remove the remaining portion of the protrusion and define a substantially planar single crystalline semiconductor layer having a substantially uniform thickness. A sacrificial layer may be formed on the single crystalline semiconductor layer and used as a polish stop for the first polishing process to define a sacrificial layer pattern, which may be removed prior to the second polishing process. Related methods of fabricating stacked semiconductor memory devices are also discussed.

摘要翻译： 制造包括沟道层的半导体器件的方法包括在半导体衬底上形成单晶半导体层。 单晶半导体层包括从其表面延伸的突起。 在单晶半导体层上执行第一抛光工艺以去除突起的一部分，使得单晶半导体层包括突起的剩余部分。 执行与第一抛光工艺不同的第二抛光工艺以去除突起的剩余部分并限定具有基本上均匀厚度的基本上平面的单晶半导体层。 可以在单晶半导体层上形成牺牲层，并且用作第一抛光工艺的抛光止挡件以限定可在第二抛光工艺之前去除的牺牲层图案。 还讨论了制造叠层半导体存储器件的相关方法。

公开(公告)号：US07670942B2

公开(公告)日：2010-03-02

申请号：US11525490

申请日：2006-09-23

申请人： Ho-Young Kim ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Joon-Sang Park

发明人： Ho-Young Kim ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Joon-Sang Park

IPC分类号： H01L21/4763

CPC分类号： H01L21/76897 ,  H01L21/7684 ,  H01L27/10873 ,  H01L27/10885

摘要： A method of fabricating a self-aligned contact pad (SAC) includes forming stacks of a conductive line and a capping layer on a semiconductor substrate, spacers covering sidewalls of the stacks, and an insulation layer filling gaps between the stacks and exposing the top of the capping layer, etching the capping layer to form damascene grooves, forming a plurality of first etching masks with a material different from that of the capping layer to fill the damascene grooves without covering the top of the insulation layer, and forming a second etching mask having an opening region that exposes some of the first etching masks and a portion of the insulation layer located between the first etching masks. The method further includes etching the portion of the insulation layer exposed by the opening region using the first and second etching masks to form a plurality of opening holes, removing the second etching mask, forming a conductive layer filling the opening holes to cover the remaining first etching masks and performing a chemical mechanical polishing (CMP) process on the conductive layer using the capping layer as a polishing end point to remove the first etching masks such that a plurality of SAC pads separated from each other are formed that fill the opening holes.

公开(公告)号：US20090001051A1

公开(公告)日：2009-01-01

申请号：US12213941

申请日：2008-06-26

申请人： Jong-Won Lee ,  Sang-Yeob Han ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Jae-Dong Lee

发明人： Jong-Won Lee ,  Sang-Yeob Han ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Jae-Dong Lee

IPC分类号： C09K13/00 ,  C23F1/04

CPC分类号： C23F3/00 ,  C09G1/02

摘要： A slurry composition for polishing metal includes a polymeric polishing accelerating agent, the polymeric polishing accelerating agent including a backbone of hydrocarbon and a side substituent having at least one of a sulfonate ion (SO3−) and a sulfate ion (OSO3−), and an acidic aqueous solution.

摘要翻译： 用于抛光金属的浆料组合物包括聚合物抛光促进剂，所述聚合物抛光促进剂包括烃的主链和具有磺酸根离子（SO 3 - ）和硫酸根离子（OSO 3 - ）中的至少一种的侧取代基， 酸性水溶液。

公开(公告)号：US20070145012A1

公开(公告)日：2007-06-28

申请号：US11542256

申请日：2006-10-04

申请人： Joon-Sang Park ,  Jong-Won Lee ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Jae-Dong Lee

发明人： Joon-Sang Park ,  Jong-Won Lee ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Jae-Dong Lee

IPC分类号： C09K13/00 ,  C03C15/00 ,  B44C1/22

CPC分类号： C09K3/1463 ,  C09G1/02 ,  H01L21/3212

摘要： Disclosed is a slurry and method for chemical-mechanical polishing operation. The slurry may contain abrasive particles, an oxidizer, a pH controller, a chelating agent and water. The viscosity of the slurry may be in the range of about 1.0 cP—about 1.05 cP, so that the step difference may be reduced between regions with patterns and without patterns even after completing the chemical-mechanical polishing operation. A permissible rate of depth of focus (DOF) may not need to be controlled in the subsequent photolithography operation, which may enable the subsequent photolithography operation to be conducted by an optical system with relatively low DOF.

摘要翻译： 公开了一种用于化学机械抛光操作的浆料和方法。 浆料可以含有磨料颗粒，氧化剂，pH控制剂，螯合剂和水。 浆料的粘度可以在约1.0cP-约1.05cP的范围内，使得即使在完成化学机械抛光操作之后，也可以在具有图案的区域与无图案的区域之间降低阶梯差。 在随后的光刻操作中可能不需要控制焦深（DOF）的允许率，这可以使得随后的光刻操作能够由具有相对低的DOF的光学系统进行。

公开(公告)号：US08766343B2

公开(公告)日：2014-07-01

申请号：US13356032

申请日：2012-01-23

申请人： Dae-Hyuk Kang ,  Bo-Un Yoon ,  Kun-Tack Lee ,  Woo-Gwan Shim ,  Ji-Hoon Cha ,  Im-Soo Park ,  Hyo-San Lee ,  Young-Hoo Kim ,  Jung-Min Oh

发明人： Dae-Hyuk Kang ,  Bo-Un Yoon ,  Kun-Tack Lee ,  Woo-Gwan Shim ,  Ji-Hoon Cha ,  Im-Soo Park ,  Hyo-San Lee ,  Young-Hoo Kim ,  Jung-Min Oh

IPC分类号： H01L27/108 ,  H01L29/94

CPC分类号： H01L28/91 ,  H01L27/10817 ,  H01L27/10852 ,  H01L28/87

摘要： In a method of forming a capacitor, a first mold layer pattern including a first insulating material may be formed on a substrate. The first mold layer pattern may have a trench. A supporting layer including a second insulating material may be formed in the trench. The second insulating material may have an etching selectivity with respect to the first insulating material. A second mold layer may be formed on the first mold layer pattern and the supporting layer pattern. A lower electrode may be formed through the second mold layer and the first mold layer pattern. The lower electrode may make contact with a sidewall of the supporting layer pattern. The first mold layer pattern and the second mold layer may be removed. A dielectric layer and an upper electrode may be formed on the lower electrode and the supporting layer pattern.

摘要翻译： 在形成电容器的方法中，可以在基板上形成包括第一绝缘材料的第一模层图案。 第一模层图案可以具有沟槽。 可以在沟槽中形成包括第二绝缘材料的支撑层。 第二绝缘材料可以具有相对于第一绝缘材料的蚀刻选择性。 可以在第一模层图案和支撑层图案上形成第二模层。 可以通过第二模具层和第一模具层图案形成下部电极。 下电极可以与支撑层图案的侧壁接触。 可以去除第一模层图案和第二模层。 电介质层和上电极可以形成在下电极和支撑层图案上。