公开(公告)号：US20140021429A1

公开(公告)日：2014-01-23

申请号：US14006424

申请日：2013-01-18

申请人： Satoru Ito ,  Satoru Fujii ,  Shinichi Yoneda ,  Takumi Mikawa

发明人： Satoru Ito ,  Satoru Fujii ,  Shinichi Yoneda ,  Takumi Mikawa

IPC分类号： H01L45/00

CPC分类号： G11C13/0007 ,  G11C2213/32 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1641

摘要： A nonvolatile memory element includes a first electrode, a second electrode, and a variable resistance layer positioned between the first electrode and the second electrode. The variable resistance layer has a resistance state which reversibly changes based on an electrical signal applied between the first electrode and the second electrode. The variable resistance layer includes a first variable resistance layer having a first metal oxide and a second variable resistance layer having a second metal oxide. The second variable resistance layer includes a metal-metal bonding region including a metal bond of metal atoms included in the second metal oxide, and the second metal oxide has a low degree of oxygen deficiency and a high resistance value compared to the first metal oxide.

摘要翻译： 非易失性存储元件包括位于第一电极和第二电极之间的第一电极，第二电极和可变电阻层。 可变电阻层具有基于施加在第一电极和第二电极之间的电信号而可逆地改变的电阻状态。 可变电阻层包括具有第一金属氧化物的第一可变电阻层和具有第二金属氧化物的第二可变电阻层。 第二可变电阻层包括与第一金属氧化物相比具有包括在第二金属氧化物中的包含金属原子的金属键的金属 - 金属结合区域，并且第二金属氧化物具有低的氧缺乏程度和高的电阻值。

公开(公告)号：US20130015522A1

公开(公告)日：2013-01-17

申请号：US13621115

申请日：2012-09-15

申请人： Toshie KUTSUNAI ,  Satoru Ito

发明人： Toshie KUTSUNAI ,  Satoru Ito

IPC分类号： H01L27/092

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7848

摘要： A semiconductor device includes an active region formed in a semiconductor substrate made of silicon, and surrounded by an isolation region; and a gate electrode formed on the active region and the isolation region with a gate insulating film interposed between the gate electrode and the active region or the isolation region. P-type silicon alloy layers are formed in recess regions formed in regions of the active region located laterally outward of the gate electrode, and an upper end of a portion of each of the silicon alloy layers in contact with the isolation region is located below a portion of an upper surface of the active region under the gate insulating film.

摘要翻译： 半导体器件包括形成在由硅制成并被隔离区域包围的半导体衬底中的有源区; 以及栅电极，形成在有源区和隔离区上，栅极绝缘膜介于栅电极和有源区或隔离区之间。 P型硅合金层形成在位于栅电极横向外侧的有源区域的区域中的凹陷区域中，与隔离区域接触的每个硅合金层的一部分的上端位于 在栅极绝缘膜下面的有源区的上表面的一部分。

公开(公告)号：US08125432B2

公开(公告)日：2012-02-28

申请号：US12195802

申请日：2008-08-21

申请人： Satoru Ito

发明人： Satoru Ito

IPC分类号： G09G3/36

CPC分类号： G11C5/147 ,  G09G3/3614 ,  G09G3/3655 ,  G11C5/145 ,  G11C29/24 ,  H02M3/07

摘要： A common voltage generation circuit includes a first operational amplifier which outputs an amplitude voltage of a common voltage based on a first power supply voltage, a second operational amplifier which outputs a high-potential-side voltage of the common voltage based on the first power supply voltage, and a low-potential-side voltage generation circuit which generates a low-potential-side voltage of the common voltage which is lower in potential than the high-potential-side voltage for the amplitude voltage by a charge-pump operation. The common voltage generation circuit supplies the high-potential-side voltage or the low-potential-side voltage to a common electrode which faces a pixel electrode specified by a scan line and a data line of an electro-optical device through an electro-optical substance.

摘要翻译： 公共电压产生电路包括基于第一电源电压输出公共电压的幅度电压的第一运算放大器，基于第一电源输出公共电压的高电位侧电压的第二运算放大器 电压和低电位侧电压产生电路，其通过电荷泵操作产生电位低于用于振幅电压的高电位侧电压的公共电压的低电位侧电压。 公共电压产生电路将高电位侧电压或低电位侧电压提供给由电光学装置的扫描线和数据线指定的像素电极的公共电极 物质。

公开(公告)号：US20120019566A1

公开(公告)日：2012-01-26

申请号：US13137995

申请日：2011-09-23

申请人： Satoru Ito ,  Masahiko Moriguchi ,  Kazuhiro Maekawa ,  Noboru Itomi ,  Satoru Kodaira ,  Junichi Karasawa ,  Takashi Kumagai ,  Hisanobu Ishiyama ,  Takashi Fujise

发明人： Satoru Ito ,  Masahiko Moriguchi ,  Kazuhiro Maekawa ,  Noboru Itomi ,  Satoru Kodaira ,  Junichi Karasawa ,  Takashi Kumagai ,  Hisanobu Ishiyama ,  Takashi Fujise

IPC分类号： G09G5/10

CPC分类号： G09G3/3688 ,  G09G3/2011 ,  G09G2330/02 ,  G09G2330/04 ,  H01L2224/05553

摘要： An integrated circuit device includes first to Nth circuit blocks CB1 to CBN, a first interface region disposed along a fourth side and on the D2 side of the first to Nth circuit blocks CB1 to CBN, and a second interface region disposed along a second side and on the D4 side of the first to Nth circuit blocks CB1 to CBN. A local line LLG formed using a wiring layer lower than an Ith layer is provided between the adjacent circuit blocks as at least one of a signal line and a power supply line. Global lines GLG and GLD formed using the Ith or higher wiring layer are provided along the direction D1 over the circuit block disposed between the nonadjacent circuit blocks as at least one of a signal line and a power supply line.

摘要翻译： 集成电路装置包括第一至第N电路块CB1至CBN，沿第一至第N电路块CB1至CBN的第四侧和第二侧设置的第一接口区域以及沿着第二侧设置的第二接口区域， 在第一至第N电路块CB1至CBN的D4侧。 使用低于第I层的布线层形成的局部线LLG设置在相邻的电路块之间，作为信号线和电源线中的至少一个。 使用第I或更高布线层形成的全局线GLG和GLD沿着方向D1设置在布置在不相邻电路块之间的电路块上，作为信号线和电源线中的至少一个。

公开(公告)号：US08076255B2

公开(公告)日：2011-12-13

申请号：US12084015

申请日：2006-10-27

申请人： Satoru Ito ,  Hitoshi Nakamura ,  Taijiro Matsui ,  Michio Nitta

发明人： Satoru Ito ,  Hitoshi Nakamura ,  Taijiro Matsui ,  Michio Nitta

IPC分类号： C04B35/101 ,  C04B35/103 ,  C04B35/66 ,  F27B9/34

CPC分类号： F27D1/0006 ,  C04B35/101 ,  C04B35/1015 ,  C04B35/66 ,  C04B41/009 ,  C04B41/5022 ,  C04B41/86 ,  C04B2235/3217 ,  C04B2235/3418 ,  C04B2235/3445 ,  C04B2235/3463 ,  C04B2235/349 ,  C04B2235/3826 ,  C04B2235/5427 ,  C04B2235/5436 ,  C04B2235/725 ,  C04B2235/80 ,  F27B9/16 ,  F27B9/34 ,  F27B9/36 ,  F27B9/39 ,  Y10T428/265 ,  C04B35/185 ,  C04B41/4539

摘要： To provide a long-life refractory capable of maintaining durability under severe conditions. The castable refractory comprises a mixture containing at least one of 2 to 10 mass % of silicon carbide and 3 to 10 mass % of chamotte, as an auxiliary raw material, and a binder material, with the remaining balance being one or more main raw materials selected from corundum, mullite, bauxite, chamotte, talc and silica, and is used in an environment exposed to an alkali component-containing hot gas atmosphere. In an alkali component-containing gas atmosphere at a high temperature (750° C. or more), silicon carbide and/or chamotte are vitrified to a thickness of 1 mm or less in the surface layer of the refractory to prevent the alkali component-containing gas from intruding inside of the refractory.

摘要翻译： 提供能够在恶劣条件下保持耐久性的长寿命耐火材料。 可浇铸耐火材料包括含有2至10质量％的碳化硅和3至10质量％的耐火砖作为辅助原料的至少一种和粘合剂材料的混合物，剩余的是一种或多种主要原料 选自刚玉，莫来石，铝土矿，氯化钙，滑石和二氧化硅，并且用于暴露于含碱成分的热气体气氛的环境中。 在高温（750℃以上）的含碱成分的气体气氛中，在耐火材料的表层中将碳化硅和/或耐火砖玻璃化至1mm以下的厚度， 含有气体从侵入耐火材料的内部。

公开(公告)号：US08054710B2

公开(公告)日：2011-11-08

申请号：US11477670

申请日：2006-06-30

申请人： Satoru Ito ,  Masahiko Moriguchi ,  Kazuhiro Maekawa ,  Noboru Itomi ,  Satoru Kodaira ,  Junichi Karasawa ,  Takashi Kumagai ,  Hisanobu Ishiyama ,  Takashi Fujise

发明人： Satoru Ito ,  Masahiko Moriguchi ,  Kazuhiro Maekawa ,  Noboru Itomi ,  Satoru Kodaira ,  Junichi Karasawa ,  Takashi Kumagai ,  Hisanobu Ishiyama ,  Takashi Fujise

IPC分类号： G11C8/00

CPC分类号： G09G3/3688 ,  G09G3/2011 ,  G09G2330/02 ,  G09G2330/04 ,  H01L2224/05553

摘要： An integrated circuit device includes first to Nth circuit blocks CB1 to CBN, a first interface region disposed along a fourth side and on the D2 side of the first to Nth circuit blocks CB1 to CBN, and a second interface region disposed along a second side and on the D4 side of the first to Nth circuit blocks CB1 to CBN. A local line LLG formed using a wiring layer lower than an Ith layer is provided between the adjacent circuit blocks as at least one of a signal line and a power supply line. Global lines GLG and GLD formed using the Ith or higher wiring layer are provided along the direction D1 over the circuit block disposed between the nonadjacent circuit blocks as at least one of a signal line and a power supply line.

摘要翻译： 集成电路装置包括第一至第N电路块CB1至CBN，沿第一至第N电路块CB1至CBN的第四侧和第二侧设置的第一接口区域以及沿着第二侧设置的第二接口区域， 在第一至第N电路块CB1至CBN的D4侧。 使用低于第I层的布线层形成的局部线LLG设置在相邻的电路块之间，作为信号线和电源线中的至少一个。 使用第I或更高布线层形成的全局线GLG和GLD沿着方向D1设置在布置在不相邻电路块之间的电路块上，作为信号线和电源线中的至少一个。

公开(公告)号：US07986541B2

公开(公告)日：2011-07-26

申请号：US11270630

申请日：2005-11-10

申请人： Satoru Kodaira ,  Noboru Itomi ,  Shuji Kawaguchi ,  Takashi Kumagai ,  Junichi Karasawa ,  Satoru Ito

发明人： Satoru Kodaira ,  Noboru Itomi ,  Shuji Kawaguchi ,  Takashi Kumagai ,  Junichi Karasawa ,  Satoru Ito

IPC分类号： G11C5/06

CPC分类号： G09G3/2007 ,  G09G2300/0426 ,  G09G2310/0267 ,  G09G2310/027 ,  G11C5/063

摘要： An integrated circuit device has a display memory which stores data for at least one frame displayed in a display panel which has a plurality of scan lines and a plurality of data lines, the display memory includes a plurality of RAM blocks, each of the RAM blocks including a plurality of wordlines, a plurality of bitlines, a plurality of memory cells, and a wordline control circuit, each of the RAM blocks is disposed along a first direction in which the bitlines extend, each of the memory cells has a short side and a long side, the bitlines are formed along a direction in which the long side of the memory cell extends, and the wordlines are formed along a direction in which the short side of the memory cell extends.

摘要翻译： 集成电路装置具有显示存储器，其存储显示在具有多条扫描线和多条数据线的显示面板中的至少一帧的数据，显示存储器包括多个RAM块，每个RAM块 包括多个字线，多个位线，多个存储器单元和字线控制电路，每个RAM块沿着位线延伸的第一方向设置，每个存储单元具有短边和 长边，沿着存储单元的长边延伸的方向形成位线，并且沿着存储单元的短边延伸的方向形成字线。

公开(公告)号：US07956833B2

公开(公告)日：2011-06-07

申请号：US11808901

申请日：2007-06-13

申请人： Satoru Ito ,  Hisanobu Ishiyama ,  Motoaki Nishimura ,  Kazuhiro Maekawa ,  Haruo Kamijo ,  Hironori Kobayashi ,  Isamu Moriya

发明人： Satoru Ito ,  Hisanobu Ishiyama ,  Motoaki Nishimura ,  Kazuhiro Maekawa ,  Haruo Kamijo ,  Hironori Kobayashi ,  Isamu Moriya

IPC分类号： G09G3/36

CPC分类号： G09G3/3655 ,  G09G3/3688 ,  G09G3/3696 ,  G09G2310/0248 ,  G09G2330/023

摘要： A display driver includes a common electrode charge storage switch provided between a first capacitor element connection node to which one end of a first capacitor element can be connected and a common electrode voltage output node to which a voltage of a common electrode opposite to a pixel electrode of an electro-optical device through an electro-optical material is supplied, a source charge storage switch provided between a second capacitor element connection node to which one end of a second capacitor element can be connected and a source voltage output node to which a voltage of a source line of the electro-optical device is supplied, and a node short circuit switch provided between the common electrode voltage output node and the source voltage output node.

摘要翻译： 显示驱动器包括公共电极电荷存储开关，其设置在可连接第一电容器元件的一端的第一电容器元件连接节点和与像素电极相对的公共电极的电压的公共电极电压输出节点之间 提供通过电光材料的电光器件的源电荷存储开关，设置在可连接第二电容器元件的一端的第二电容器元件连接节点与源电压输出节点之间的电压存储开关， 提供电光装置的源极线，以及设置在公共电极电压输出节点和源电压输出节点之间的节点短路开关。

公开(公告)号：US20100294326A1

公开(公告)日：2010-11-25

申请号：US12864068

申请日：2009-01-22

申请人： Junqing Guo ,  Shunichi Ochi ,  Huiyuan Geng ,  Takahiro Ochi ,  Satoru Ito

发明人： Junqing Guo ,  Shunichi Ochi ,  Huiyuan Geng ,  Takahiro Ochi ,  Satoru Ito

IPC分类号： H01L35/16

摘要： The present invention realizes a thermoelectric conversion material having excellent thermoelectric performance over a wide temperature range, and a thermoelectric conversion module providing excellent junctions between thermoelectric conversion materials and electrodes.The present invention provides an R-T-M-X-N thermoelectric conversion material that has a structure expressed by the following formula: RrTt−mMmXx−nNn (0

摘要翻译： 本发明实现了在宽的温度范围内具有优异的热电性能的热电转换材料和提供热电转换材料和电极之间的良好接合的热电转换模块。 本发明提供一种RTMXN热电转换材料，其具有由下式表示的结构：RrTt-mMmXx-nNn（0

公开(公告)号：US20090091580A1

公开(公告)日：2009-04-09

申请号：US12292996

申请日：2008-12-02

申请人： Satoru Kodaira ,  Noboru Itomi ,  Shuji Kawaguchi ,  Takashi Kumagai ,  Junichi Karasawa ,  Satoru Ito

发明人： Satoru Kodaira ,  Noboru Itomi ,  Shuji Kawaguchi ,  Takashi Kumagai ,  Junichi Karasawa ,  Satoru Ito

IPC分类号： G09G5/39

CPC分类号： G09G3/3685 ,  G09G3/20 ,  G09G3/3611 ,  G09G5/39 ,  G09G5/395 ,  G09G2300/0426 ,  G09G2310/0218 ,  G09G2310/027 ,  G09G2310/0278 ,  G09G2360/12

摘要： An integrated circuit device having a display memory which stores data for at least one frame from among image information displayed in a display panel which has a plurality of scan lines and a plurality of data lines, the display memory including a plurality of wordlines, a plurality of bitlines, a plurality of memory cells, and a wordline control circuit; and the wordline control circuit selecting an identical wordline N times (N is an integer larger than one) from among the wordlines in one horizontal scan period of the display panel.

摘要翻译： 一种具有显示存储器的集成电路装置，该显示存储器从显示在具有多个扫描线和多条数据线的显示面板中的图像信息中存储至少一帧的数据，所述显示存储器包括多个字线，多个 位线，多个存储单元和字线控制电路; 并且字线控制电路在显示面板的一个水平扫描周期中从字线中选择相同的字线N次（N是大于1的整数）。