公开(公告)号：US20120104619A1

公开(公告)日：2012-05-03

申请号：US12913116

申请日：2010-10-27

申请人： Shom Ponoth ,  David V. Horak ,  Chih-Chao Yang

发明人： Shom Ponoth ,  David V. Horak ,  Chih-Chao Yang

IPC分类号： H01L23/52 ,  H01L21/768

CPC分类号： H01L23/5226 ,  H01L21/02126 ,  H01L21/3105 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76807 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A first low dielectric constant (low-k) dielectric material layer is lithographically patterned to form a recessed region having expose substantially vertical sidewalls, which are subsequently damaged to de-carbonize a surface portion at the sidewalls having a sublithographic width. A second low-k dielectric material layer is deposited to fill the recessed region and planarized to exposed top surfaces of the damaged low-k dielectric material portion. The damaged low-k dielectric material portion is removed selective to the first and second low-k dielectric material layers to form a trench with a sublithographic width. A portion of the pattern of the sublithographic-width trench is transferred into a metallic layer and optionally to an underlying dielectric masking material layer to define a trench with a sublithographic width, which can be employed as a template to confine the widths of via holes and line trenches to be subsequently formed in an interconnect-level dielectric material layer.

摘要翻译： 第一低介电常数（低k）电介质材料层被光刻图案化以形成具有暴露基本上垂直侧壁的凹陷区域，其随后被损坏以使具有亚光刻宽度的侧壁处的表面部分脱碳。 沉积第二低k电介质材料层以填充凹陷区域并平坦化到损坏的低k电介质材料部分的暴露的顶表面。 选择性地去除损坏的低k电介质材料部分到第一和第二低k电介质材料层以形成具有亚光刻宽度的沟槽。 亚光刻宽度沟槽的图案的一部分被转移到金属层中，并且可选地转移到下面的介电掩模材料层以限定具有亚光刻宽度的沟槽，其可以用作模板以限制通孔的宽度和 随后在互连级介电材料层中形成线沟槽。

公开(公告)号：US07928570B2

公开(公告)日：2011-04-19

申请号：US12424843

申请日：2009-04-16

申请人： Shom Ponoth ,  David V. Horak ,  Takeshi Nogami ,  Chih-Chao Yang

发明人： Shom Ponoth ,  David V. Horak ,  Takeshi Nogami ,  Chih-Chao Yang

IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L23/538

CPC分类号： H01L21/76847 ,  H01L21/76805 ,  H01L21/76846 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure is disclosed. In one embodiment, the interconnect structure includes: a substrate including a first liner layer and a first metal layer thereover; a dielectric barrier layer over the first metal layer and the substrate; an inter-level dielectric layer over the dielectric barrier layer; a via extending between the inter-level dielectric layer, the dielectric barrier layer, and the first metal layer, the via including a second liner layer and a second metal layer thereover; and a diffusion barrier layer located between the second liner layer and the first metal layer, wherein a portion of the diffusion barrier layer is located under the dielectric barrier layer.

摘要翻译： 公开了互连结构。 在一个实施例中，互连结构包括：衬底，其包括第一衬里层和其上的第一金属层; 在所述第一金属层和所述衬底上的介电阻挡层; 电介质阻挡层上的层间电介质层; 所述通孔在所述层间电介质层，所述电介质阻挡层和所述第一金属层之间延伸，所述通孔在其上包括第二衬垫层和第二金属层; 以及位于所述第二衬垫层和所述第一金属层之间的扩散阻挡层，其中所述扩散阻挡层的一部分位于所述电介质阻挡层下方。

公开(公告)号：US20090309226A1

公开(公告)日：2009-12-17

申请号：US12139704

申请日：2008-06-16

申请人： David V. Horak ,  Shom Ponoth ,  Chih-Chao Yang

发明人： David V. Horak ,  Shom Ponoth ,  Chih-Chao Yang

IPC分类号： H01L23/48 ,  H01L21/4763

CPC分类号： H01L23/5226 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76849 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure having enhanced electromigration resistance is provided in which a lower portion of a via opening includes a multi-layered liner. The multi-layered liner includes, from a patterned surface of a dielectric material outwards, a diffusion barrier, a multi-material layer and a metal-containing hard mask. The multi-material layer includes a first material layer comprised of residue from an underlying dielectric capping layer, and a second material layer comprised of residue from an underlying metallic capping layer. The present invention also provides a method of fabricating such an interconnect structure which includes the multi-layered liner within a lower portion of a via opening formed within a dielectric material.

摘要翻译： 提供具有增强的电迁移阻力的互连结构，其中通路孔的下部包括多层衬垫。 多层衬垫包括从电介质材料的图案化表面向外扩散阻挡层，多材料层和含金属硬掩模。 多材料层包括由下面的电介质覆盖层的残留物构成的第一材料层和由下面的金属覆盖层的残留物构成的第二材料层。 本发明还提供一种制造这种互连结构的方法，其包括在介电材料内形成的通路孔的下部内的多层衬垫。

公开(公告)号：US08946006B2

公开(公告)日：2015-02-03

申请号：US12913922

申请日：2010-10-28

申请人： Shom Ponoth ,  David V. Horak ,  Chih-Chao Yang

发明人： Shom Ponoth ,  David V. Horak ,  Chih-Chao Yang

IPC分类号： H01L21/00 ,  H01L29/78 ,  H01L29/66

CPC分类号： H01L29/78 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66628 ,  H01L29/7834

摘要： A disposable dielectric spacer is formed on sidewalls of a disposable material stack. Raised source/drain regions are formed on planar source/drain regions by selective epitaxy. The disposable dielectric spacer is removed to expose portions of a semiconductor layer between the disposable material stack and the source/drain regions including the raised source/drain regions. Dopant ions are implanted to form source/drain extension regions in the exposed portions of the semiconductor layer. A gate-level dielectric layer is deposited and planarized. The disposable material stack is removed and a gate stack including a gate dielectric and a gate electrode fill a cavity formed by removal of the disposable material stack. Optionally, an inner dielectric spacer may be formed on sidewalls of the gate-level dielectric layer within the cavity prior to formation of the gate stack to tailor a gate length of a field effect transistor.

公开(公告)号：US08399350B2

公开(公告)日：2013-03-19

申请号：US12700792

申请日：2010-02-05

申请人： Takeshi Nogami ,  Shyng-Tsong Chen ,  David V. Horak ,  Son V. Nguyen ,  Shom Ponoth ,  Chih-Chao Yang

发明人： Takeshi Nogami ,  Shyng-Tsong Chen ,  David V. Horak ,  Son V. Nguyen ,  Shom Ponoth ,  Chih-Chao Yang

IPC分类号： H01L21/4763

CPC分类号： H01L24/80 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295

摘要： Method for fabricating a microelectronic element having an air gap in a dielectric layer thereof. A dielectric cap layer can be formed which has a first portion overlying surfaces of metal lines, the first portion extending a first height above a height of a surface of the dielectric layer, and a second portion overlying the dielectric layer surface and extending a second height above the height of the surface of the dielectric layer, the second height being greater than the first height. After forming the cap layer, a mask can be formed over the cap layer. The mask exposes a surface of only the second portion of the cap layer which has the greater height. Subsequently, an etchant can be directed towards the first and second portions of the cap layer. Material can be removed from the dielectric layer where exposed to the etchant.

摘要翻译： 一种在其电介质层中具有气隙的微电子元件的制造方法。 可以形成介电盖层，其具有覆盖金属线表面的第一部分，第一部分在电介质层表面的高度之上延伸第一高度，以及覆盖介电层表面的第二部分，并延伸第二高度 高于介电层表面的高度，第二高度大于第一高度。 在形成盖层之后，可以在盖层之上形成掩模。 掩模仅暴露具有较大高度的盖层的第二部分的表面。 随后，蚀刻剂可以被引导到盖层的第一和第二部分。 材料可以从暴露于蚀刻剂的介电层去除。

公开(公告)号：US20120190187A1

公开(公告)日：2012-07-26

申请号：US13431254

申请日：2012-03-27

申请人： Chih-Chao Yang ,  David V. Horak ,  Takeshi Nogami ,  Shom Ponoth

发明人： Chih-Chao Yang ,  David V. Horak ,  Takeshi Nogami ,  Shom Ponoth

IPC分类号： H01L21/768

CPC分类号： H01L24/80 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/82 ,  H01L24/92 ,  H01L25/50 ,  H01L2224/05007 ,  H01L2224/05014 ,  H01L2224/0502 ,  H01L2224/05099 ,  H01L2224/05547 ,  H01L2224/05554 ,  H01L2224/0556 ,  H01L2224/05599 ,  H01L2224/08121 ,  H01L2224/80001 ,  H01L2224/80345 ,  H01L2224/80357 ,  H01L2224/80359 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/821 ,  H01L2224/9212 ,  H01L2225/06513 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/00 ,  H01L2224/80 ,  H01L2224/82

摘要： Two substrates are brought together and placed in a plating bath. In one embodiment, a conductive material is plated in microscopic cavities present at the interface between a first metal pad and a second metal pad to form at least one interfacial plated metal liner portion that adheres to a surface of the first metal pad and a surface of the second metal pad. In another embodiment, at least one metal pad is recessed relative to a dielectric surface before being brought together. The two substrates are placed in a plating bath and a conductive material is plated in the cavity between the first metal pad and the second metal pad to form a contiguous plated metal liner layer that adheres to a surface of the first metal pad and a surface of the second metal pad.

摘要翻译： 将两个基材放在一起并放置在电镀浴中。 在一个实施例中，将导电材料电镀在存在于第一金属焊盘和第二金属焊盘之间的界面处的微观空腔中，以形成粘附到第一金属焊盘表面的至少一个界面电镀金属衬垫部分， 第二个金属垫。 在另一个实施例中，至少一个金属焊盘相对于电介质表面在被聚集之前是凹进的。 将两个基板放置在电镀槽中，并且将导电材料镀在第一金属焊盘和第二金属焊盘之间的空腔中，以形成附着在第一金属焊盘的表面上的连续的电镀金属衬垫层， 第二个金属垫。

公开(公告)号：US20120171859A1

公开(公告)日：2012-07-05

申请号：US13415164

申请日：2012-03-08

申请人： Shom Ponoth ,  David V. Horak ,  Takeshi Nogami ,  Chih-Chao Yang

发明人： Shom Ponoth ,  David V. Horak ,  Takeshi Nogami ,  Chih-Chao Yang

IPC分类号： H01L21/768

CPC分类号： H01L23/5226 ,  H01L21/31116 ,  H01L21/768 ,  H01L21/76816 ,  H01L21/76829 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of the invention provide a method of creating vias and trenches with different length. The method includes depositing a plurality of dielectric layers on top of a semiconductor structure with the plurality of dielectric layers being separated by at least one etch-stop layer; creating multiple openings from a top surface of the plurality of dielectric layers down into the plurality of dielectric layers by a non-selective etching process, wherein at least one of the multiple openings has a depth below the etch-step layer; and continuing etching the multiple openings by a selective etching process until one or more openings of the multiple openings that are above the etch-stop layer reach and expose the etch-stop layer. Semiconductor structures made thereby are also provided.

摘要翻译： 本发明的实施例提供了一种创建具有不同长度的通孔和沟槽的方法。 该方法包括在半导体结构的顶部上沉积多个电介质层，多个电介质层被至少一个蚀刻停止层隔开; 通过非选择性蚀刻工艺从所述多个电介质层的顶表面形成多个开口到多个介电层中，其中所述多个开口中的至少一个具有在所述蚀刻步骤层下方的深度; 以及通过选择性蚀刻工艺继续蚀刻多个开口，直到位于蚀刻停止层上方的多个开口的一个或多个开口到达和暴露蚀刻停止层。 还提供了由此制成的半导体结构。

公开(公告)号：US20120104470A1

公开(公告)日：2012-05-03

申请号：US12913922

申请日：2010-10-28

申请人： Shom Ponoth ,  David V. Horak ,  Chih-Chao Yang

发明人： Shom Ponoth ,  David V. Horak ,  Chih-Chao Yang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/78 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66628 ,  H01L29/7834

摘要： A disposable dielectric spacer is formed on sidewalls of a disposable material stack. Raised source/drain regions are formed on planar source/drain regions by selective epitaxy. The disposable dielectric spacer is removed to expose portions of a semiconductor layer between the disposable material stack and the source/drain regions including the raised source/drain regions. Dopant ions are implanted to form source/drain extension regions in the exposed portions of the semiconductor layer. A gate-level dielectric layer is deposited and planarized. The disposable material stack is removed and a gate stack including a gate dielectric and a gate electrode fill a cavity formed by removal of the disposable material stack. Optionally, an inner dielectric spacer may be formed on sidewalls of the gate-level dielectric layer within the cavity prior to formation of the gate stack to tailor a gate length of a field effect transistor.

摘要翻译： 一次性介电隔离件形成在一次性材料堆叠的侧壁上。 通过选择性外延在平坦的源极/漏极区域上形成升高的源极/漏极区域。 去除一次性电介质间隔物以暴露一次性材料堆叠和包括升高的源极/漏极区域的源极/漏极区域之间的半导体层的部分。 注入掺杂离子以在半导体层的暴露部分中形成源极/漏极延伸区域。 沉积栅平电介质层并进行平面化。 去除一次性材料堆叠并且包括栅极电介质和栅电极的栅极堆叠填充通过去除一次性材料堆而形成的空腔。 可选地，可以在形成栅极叠层之前在腔内的栅极级介电层的侧壁上形成内部电介质间隔物，以调整场效应晶体管的栅极长度。

公开(公告)号：US08008669B2

公开(公告)日：2011-08-30

申请号：US12509892

申请日：2009-07-27

申请人： Chih-Chao Yang ,  David V. Horak ,  Takeshi Nogami ,  Shom Ponoth

发明人： Chih-Chao Yang ,  David V. Horak ,  Takeshi Nogami ,  Shom Ponoth

IPC分类号： H01L29/15

CPC分类号： H01L23/5252 ,  H01L23/53276 ,  H01L2924/0002 ,  H01L2924/00

摘要： In one embodiment an anti-fuse structure is provided that includes a first dielectric material having at least a first anti-fuse region and a second anti-fuse region, wherein at least one of the anti-fuse regions includes a conductive region embedded within the first dielectric material. The anti-fuse structure further includes a first diamond like carbon layer having a first conductivity located on at least the first dielectric material in the first anti-fuse region and a second diamond like carbon layer having a second conductivity located on at least the first dielectric material in the second anti-fuse region. In this embodiment, the second conductivity is different from the first conductivity and the first diamond like carbon layer and the second diamond like carbon layer have the same thickness. The anti-fuse structure also includes a second dielectric material located atop the first and second diamond like carbon layers. The second dielectric material includes at least one conductively filled region embedded therein.

摘要翻译： 在一个实施例中，提供了一种抗熔丝结构，其包括具有至少第一抗熔融区域和第二抗熔融区域的第一电介质材料，其中至少一个反熔丝区域包括嵌入在该熔断区域内的导电区域 第一电介质材料。 反熔丝结构还包括第一金刚石碳层，其具有位于第一抗熔融区域中的至少第一电介质材料上的第一导电性，第二类金刚石碳层具有位于至少第一电介质上的第二导电性 材料在第二个反熔丝区域。 在本实施例中，第二导电率不同于第一导电性，第一类金刚石碳层和第二类金刚石碳层具有相同的厚度。 反熔丝结构还包括位于第一和第二金刚石状碳层顶上的第二电介质材料。 第二电介质材料包括嵌入其中的至少一个导电填充区域。

公开(公告)号：US20110163450A1

公开(公告)日：2011-07-07

申请号：US12652485

申请日：2010-01-05

申请人： David V. Horak ,  Takeshi Nogami ,  Shom Ponoth ,  Chih-Chao Yang

发明人： David V. Horak ,  Takeshi Nogami ,  Shom Ponoth ,  Chih-Chao Yang

IPC分类号： H01L23/50 ,  H01L21/768

CPC分类号： H01L23/53238 ,  H01L21/76834 ,  H01L21/76847 ,  H01L21/76852 ,  H01L21/76885 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating an integrated circuit comprising an electromigration barrier in a line of the integrated circuit includes forming a spacer; forming a segmented line adjacent to opposing sides of the spacer, the segmented line formed from a first conductive material; removing the spacer to form an empty line break; and filling the empty line break with a second conductive material to form an electromigration barrier that isolates electromigration effects within individual segments of the segmented line. An integrated circuit comprising an electromigration barrier includes a line, the line comprising a first conductive material, the line further comprising a plurality of line segments separated by one or more electromigration barriers, wherein the one or more electromigration barriers comprise a second conductive material that isolates electromigration effects within individual segments of the line.

摘要翻译： 一种用于制造集成电路的集成电路的方法，包括：集成电路的一行中的电迁移势垒包括形成间隔物; 形成与所述间隔物的相对侧相邻的分段线，所述分段线由第一导电材料形成; 移除间隔物以形成空线断裂; 并用第二导电材料填充空线断裂以形成电隔离屏蔽，其隔离分段线的各个段内的电迁移效应。 包括电迁移屏障的集成电路包括线，该线包括第一导电材料，该线还包括由一个或多个电迁移屏障隔开的多个线段，其中所述一个或多个电迁移屏障包括隔离的第二导电材料 线路各部分的电迁移效应。