公开(公告)号：US20230244611A1

公开(公告)日：2023-08-03

申请号：US18083703

申请日：2022-12-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok Chachad ,  Raguram Damodaran ,  Ramakrishnan Venkatasubramanian ,  Joseph Raymond Michael Zbiciak

IPC: G06F12/1081 ,  G06F7/483 ,  G06F9/30 ,  H03M13/35 ,  H03M13/29 ,  G06F11/10 ,  G06F13/16 ,  G06F13/18 ,  H03K19/00 ,  G06F1/3296 ,  H03K21/00 ,  G06F12/02 ,  G06F12/12 ,  G06F12/0811 ,  G06F12/0815

CPC classification number: G06F12/1081 ,  G06F7/483 ,  G06F9/3012 ,  H03M13/353 ,  H03M13/2903 ,  G06F11/1064 ,  G06F13/1605 ,  G06F13/18 ,  H03K19/0016 ,  G06F1/3296 ,  H03K21/00 ,  G06F12/0246 ,  G06F12/12 ,  G06F12/0811 ,  G06F12/0815 ,  G06F13/1652 ,  G06F13/1657 ,  G06F13/1663 ,  G06F13/364

Abstract: A queuing requester for access to a memory system is provided. Transaction requests are received from two or more requestors for access to the memory system. Each transaction request includes an associated priority value. A request queue of the received transaction requests is formed in the queuing requester. Each transaction request includes an associated priority value. A highest priority value of all pending transaction requests within the request queue is determined. An elevated priority value is selected when the highest priority value is higher than the priority value of an oldest transaction request in the request queue; otherwise the priority value of the oldest transaction request is selected. The oldest transaction request in the request queue with the selected priority value is then provided to the memory system. An arbitration contest with other requesters for access to the memory system is performed using the selected priority value.

公开(公告)号：US11681532B2

公开(公告)日：2023-06-20

申请号：US16846686

申请日：2020-04-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David Anderson ,  Duc Quang Bui ,  Joseph Raymond Michael Zbiciak

IPC: G06F9/30 ,  G06F9/38 ,  G06F7/499 ,  G06F15/80

CPC classification number: G06F9/30167 ,  G06F9/3016 ,  G06F9/30181 ,  G06F9/3822 ,  G06F9/3853 ,  G06F7/49994 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3836 ,  G06F15/8053

Abstract: In a very long instruction word (VLIW) central processing unit instructions are grouped into execute packets that execute in parallel. A constant may be specified or extended by bits in a constant extension instruction in the same execute packet. If an instruction includes an indication of constant extension, the decoder employs bits of a constant extension instruction to extend the constant of an immediate field. Two or more constant extension slots are permitted in each execute packet, each extending constants for a different predetermined subset of functional unit instructions. In an alternative embodiment, more than one functional unit may have constants extended from the same constant extension instruction employing the same extended bits. A long extended constant may be formed using the extension bits of two constant extension instructions.

公开(公告)号：US20230168890A1

公开(公告)日：2023-06-01

申请号：US18097552

申请日：2023-01-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David Anderson ,  Duc Quang Bui ,  Mujibur Rahman ,  Joseph Raymond Michael Zbiciak ,  Eric Biscondi ,  Peter Dent ,  Jelena Milanovic ,  Ashish Shrivastava

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30036 ,  G06F9/3893 ,  G06F9/30021 ,  G06F9/30018 ,  G06F9/3001 ,  G06F9/30112

Abstract: A Very Long Instruction Word (VLIW) digital signal processor particularly adapted for single instruction multiple data (SIMD) operation on various operand widths and data sizes. A vector compare instruction compares first and second operands and stores compare bits. A companion vector conditional instruction performs conditional operations based upon the state of a corresponding predicate data register bit. A predicate unit performs data processing operations on data in at least one predicate data register including unary operations and binary operations. The predicate unit may also transfer data between a general data register file and the predicate data register file.

公开(公告)号：US11042468B2

公开(公告)日：2021-06-22

申请号：US16181894

申请日：2018-11-06

Applicant: Texas Instruments Incorporated

Inventor： Joseph Raymond Michael Zbiciak ,  Jason Lynn Peck

IPC: G06F11/00 ,  G06F11/36 ,  G06F9/54

Abstract: A method for debugging a software program is provided when the software program is executed on a processor. An asynchronous debug event is detected. The asynchronous debug event is tracked through a data pipeline to the processor. In one embodiment, the asynchronous debug event is acted on only when the processor is ready to consume a data element associated with the asynchronous debug event.

公开(公告)号：US10963254B2

公开(公告)日：2021-03-30

申请号：US16290872

申请日：2019-03-02

Applicant: Texas Instruments Incorporated

Inventor： Timothy David Anderson ,  Jonathan (Son) Hung Tran ,  Joseph Raymond Michael Zbiciak

IPC: G06F9/34 ,  G06F11/00 ,  G06F12/02 ,  G06F9/30 ,  G06F9/38 ,  G06F11/10 ,  G06F9/32 ,  G06F12/0875 ,  G06F12/0897 ,  G06F9/345

Abstract: A steaming engine in a system receives a first set of stream parameters into a queue to define a first stream along with an indication of either a queue mode of operation or a speculative mode of operation for the first stream. Acquisition of the first stream then begins. At some point, a second set of stream parameters is received into the queue to define a second stream. When the queue mode of operation was specified for the first stream, the second set of parameters is queued and acquisition of the second stream is delayed until completion of acquisition of the first stream. When the speculative mode of operation was specified for the first stream, acquisition of the first stream is canceled upon receipt of the second set of stream parameters and acquisition of the second stream begins immediately.

公开(公告)号：US10936315B2

公开(公告)日：2021-03-02

申请号：US16237547

申请日：2018-12-31

Applicant: Texas Instruments Incorporated

Inventor： Duc Quang Bui ,  Joseph Raymond Michael Zbiciak

IPC: G06F9/30 ,  G06F9/40 ,  G06F15/76 ,  G06F9/38 ,  G06F15/78 ,  G06F9/32

Abstract: In a method of operating a computer system, an instruction loop is executed by a processor in which each iteration of the instruction loop accesses a current data vector and an associated current vector predicate. The instruction loop is repeated when the current vector predicate indicates the current data vector contains at least one valid data element and the instruction loop is exited when the current vector predicate indicates the current data vector contains no valid data elements.

公开(公告)号：US20200326941A1

公开(公告)日：2020-10-15

申请号：US16861347

申请日：2020-04-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Raymond Michael Zbiciak

IPC: G06F9/30 ,  G06F9/345 ,  G06F11/10 ,  G06F9/32 ,  G06F9/38 ,  G06F12/0875 ,  G06F12/0897 ,  G06F11/00

Abstract: A stream of data is accessed from a memory system by an autonomous memory access engine, converted on the fly by the memory access engine, and then presented to a processor for data processing. A portion of a lookup table (LUT) containing converted data elements is preloaded into a lookaside buffer associated with the memory access engine. As the stream of data elements is fetched from the memory system each data element in the stream of data elements is replaced with a respective converted data element obtained from the LUT in the lookaside buffer according to a content of each data element to thereby form a stream of converted data elements. The stream of converted data elements is then propagated from the memory access engine to a data processor.

公开(公告)号：US20200310807A1

公开(公告)日：2020-10-01

申请号：US16846686

申请日：2020-04-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David Anderson ,  Duc Quang Bui ,  Joseph Raymond Michael Zbiciak

IPC: G06F9/30 ,  G06F9/38

Abstract: In a very long instruction word (VLIW) central processing unit instructions are grouped into execute packets that execute in parallel. A constant may be specified or extended by bits in a constant extension instruction in the same execute packet. If an instruction includes an indication of constant extension, the decoder employs bits of a constant extension instruction to extend the constant of an immediate field. Two or more constant extension slots are permitted in each execute packet, each extending constants for a different predetermined subset of functional unit instructions. In an alternative embodiment, more than one functional unit may have constants extended from the same constant extension instruction employing the same extended bits. A long extended constant may be formed using the extension bits of two constant extension instructions.

公开(公告)号：US10713180B2

公开(公告)日：2020-07-14

申请号：US15991241

申请日：2018-05-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok Chachad ,  Raguram Damodaran ,  Ramakrishnan Venkatasubramanian ,  Joseph Raymond Michael Zbiciak

IPC: G06F9/30 ,  G06F12/1081 ,  G06F7/483 ,  H03M13/35 ,  H03M13/29 ,  G06F11/10 ,  G06F13/16 ,  G06F13/18 ,  H03K19/00 ,  G06F1/3296 ,  H03K21/00 ,  G06F12/02 ,  G06F12/12 ,  G06F12/0811 ,  G06F12/0815 ,  G06F13/364

Abstract: A queuing requester for access to a memory system is provided. Transaction requests are received from two or more requestors for access to the memory system. Each transaction request includes an associated priority value. A request queue of the received transaction requests is formed in the queuing requester. Each transaction request includes an associated priority value. A highest priority value of all pending transaction requests within the request queue is determined. An elevated priority value is selected when the highest priority value is higher than the priority value of an oldest transaction request in the request queue; otherwise the priority value of the oldest transaction request is selected. The oldest transaction request in the request queue with the selected priority value is then provided to the memory system. An arbitration contest with other requesters for access to the memory system is performed using the selected priority value.

公开(公告)号：US10649775B2

公开(公告)日：2020-05-12

申请号：US16206091

申请日：2018-11-30

Applicant: Texas Instruments Incorporated

Inventor： Joseph Raymond Michael Zbiciak

IPC: G06F9/312 ,  G06F5/00 ,  G06F12/00 ,  G06F9/30 ,  G06F9/345 ,  G06F11/10 ,  G06F9/32 ,  G06F9/38 ,  G06F12/0875 ,  G06F12/0897 ,  G06F11/00 ,  G06F5/06

Abstract: A stream of data is accessed from a memory system by an autonomous memory access engine, converted on the fly by the memory access engine, and then presented to a processor for data processing. A portion of a lookup table (LUT) containing converted data elements is preloaded into a lookaside buffer associated with the memory access engine. As the stream of data elements is fetched from the memory system each data element in the stream of data elements is replaced with a respective converted data element obtained from the LUT in the lookaside buffer according to a content of each data element to thereby form a stream of converted data elements. The stream of converted data elements is then propagated from the memory access engine to a data processor.