公开(公告)号：US12237417B2

公开(公告)日：2025-02-25

申请号：US18061862

申请日：2022-12-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Yin Chen ,  Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L21/82 ,  H01L21/3213 ,  H01L21/66 ,  H01L21/67 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  G01N21/88

Abstract: A FinFET structure with a gate structure having two notch features therein and a method of forming the same is disclosed. The FinFET notch features ensure that sufficient spacing is provided between the gate structure and source/drain regions of the FinFET to avoid inadvertent shorting of the gate structure to the source/drain regions. Gate structures of different sizes (e.g., different gate widths) and of different pattern densities can be provided on a same substrate and avoid inadvertent of shorting the gate to the source/drain regions through application of the notched features.

公开(公告)号：US12211750B2

公开(公告)日：2025-01-28

申请号：US17808709

申请日：2022-06-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chang-Yin Chen ,  Jr-Jung Lin ,  Chih-Han Lin ,  Yung-Jung Chang

IPC: H01L21/8234 ,  H01L21/3213 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/088 ,  H01L27/12 ,  H01L29/78

Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a substrate. The semiconductor device also includes a first fin and a second fin over the substrate. The semiconductor device further includes a first gate electrode and a second gate electrode traversing over the first fin and the second fin, respectively. In addition, the semiconductor device includes a gate dielectric layer between the first fin and the first gate electrode and between the second fin and the second gate electrode. Further, the semiconductor device includes a dummy gate electrode over the substrate, and the dummy gate electrode is between the first gate electrode and the second gate electrode. An upper portion of the dummy gate electrode is wider than a lower portion of the dummy gate electrode.

公开(公告)号：US12206011B2

公开(公告)日：2025-01-21

申请号：US18354995

申请日：2023-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Chih-Han Lin ,  Shu-Uei Jang ,  Ya-Yi Tsai ,  Shu-Yuan Ku

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088

Abstract: A method includes forming a dummy gate stack, etching the dummy gate stack to form an opening, depositing a first dielectric layer extending into the opening, and depositing a second dielectric layer on the first dielectric layer and extending into the opening. A planarization process is then performed to form a gate isolation region including the first dielectric layer and the second dielectric layer. The dummy gate stack is then removed to form trenches on opposing sides of the gate isolation region. The method further includes performing a first etching process to remove sidewall portions of the first dielectric layer, performing a second etching process to thin the second dielectric layer, and forming replacement gates in the trenches.

公开(公告)号：US12176415B2

公开(公告)日：2024-12-24

申请号：US17814756

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Chih-Han Lin

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/51 ,  H01L29/78

Abstract: A method includes forming an active channel region, forming a dummy channel region, forming a first gate dielectric layer over the active channel region, forming a second gate dielectric layer over the dummy channel region, removing the second gate dielectric layer from the dummy channel region, forming a gate isolation region over and contacting the dummy channel region, and forming a first gate stack and a second gate stack. The first gate stack is on the active channel region. The gate isolation region separates the first gate stack from the second gate stack.

公开(公告)号：US20240379672A1

公开(公告)日：2024-11-14

申请号：US18780798

申请日：2024-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Sheng Lai ,  Wei-Chung Sun ,  Li-Ting Chen ,  Kuei-Yu Kao ,  Chih-Han Lin

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

Abstract: A device includes a plurality of fin structures that each protrude vertically upwards out of a substrate and each extend in a first direction in a top view. A gate structure is disposed over the fin structures. The gate structure extends in a second direction in the top view. The second direction is different from the first direction. The fin structures have a fin pitch equal to a sum of: a dimension of one of the fin structures in the second direction and a distance between an adjacent pair of the fin structures in the second direction. An end segment of the gate structure extends beyond an edge of a closest one of the fin structures in the second direction. The end segment has a tapered profile in the top view or is at least 4 times as long as the fin pitch in the second direction.

公开(公告)号：US12087638B2

公开(公告)日：2024-09-10

申请号：US18334918

申请日：2023-06-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Chih-Chung Chiu ,  Kuei-Yu Kao ,  Chen-Ping Chen ,  Chih-Han Lin

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/3065 ,  H01L27/088 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L21/823462 ,  H01L21/02532 ,  H01L21/3065 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/42392 ,  H01L29/66795 ,  H01L27/088

Abstract: The disclosure is directed towards semiconductor devices and methods of manufacturing the semiconductor devices. The methods include forming fins in a device region and forming other fins in a multilayer stack of semiconductor materials in a multi-channel device region. A topmost nanostructure may be exposed in the multi-channel device region by removing a sacrificial layer from the top of the multilayer stack. Once removed, a stack of nanostructures are formed from the multilayer stack. A native oxide layer is formed to a first thickness over the topmost nanostructure and to a second thickness over the remaining nanostructures of the stack, the first thickness being greater than the second thickness. A gate dielectric is formed over the fins in the device region. A gate electrode is formed over the gate dielectric in the device region and surrounding the native oxide layer in the multi-channel device region.

公开(公告)号：US20240154025A1

公开(公告)日：2024-05-09

申请号：US18409398

申请日：2024-01-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Kuei-Yu Kao ,  Chih-Han Lin ,  Ming-Ching Chang ,  Chao-Cheng Chen

IPC: H01L29/66 ,  H01L21/306 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/30621 ,  H01L21/823431 ,  H01L29/66795 ,  H01L29/7856 ,  H01L2029/7858

Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming isolation regions on opposing sides of the fin; forming a dummy gate electrode over the fin; removing lower portions of the dummy gate electrode proximate to the isolation regions, where after removing the lower portions, there is a gap between the isolation regions and a lower surface of the dummy gate electrode facing the isolation regions; filling the gap with a gate fill material; after filling the gap, forming gate spacers along sidewalls of the dummy gate electrode and along sidewalls of the gate fill material; and replacing the dummy gate electrode and the gate fill material with a metal

公开(公告)号：US11935889B2

公开(公告)日：2024-03-19

申请号：US17097423

申请日：2020-11-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L27/08 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/088 ,  H01L27/12 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/66545

Abstract: A method includes, in a first etching step, etching a semiconductor substrate to form first recesses in a first device region and second recesses in a second device regions simultaneously. A first semiconductor strip is formed between the first recesses. A second semiconductor strip is formed between the second recesses. In a second etching step, the semiconductor substrate in the second device region is etched to extend the second recesses. The first recesses and the second recesses are filled with a dielectric material to form first and second isolation regions in the first and second recesses, respectively. The first isolation regions and the second isolation regions are recessed. Portions of the semiconductor substrate in the first and the second device regions protrude higher than top surfaces of the respective first and second isolation regions to form a first and a second semiconductor fin, respectively.

公开(公告)号：US11894274B2

公开(公告)日：2024-02-06

申请号：US17809953

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Te-Yung Liu ,  Chih-Han Lin

IPC: H01L21/8234 ,  H01L27/088 ,  H01L27/092

CPC classification number: H01L21/823431 ,  H01L21/823418 ,  H01L27/0886 ,  H01L27/0924

Abstract: A method includes forming a first protruding semiconductor fin and a dummy fin protruding higher than top surfaces of isolation regions. The first protruding semiconductor fin is parallel to the dummy fin, forming a gate stack on a first portion of the first protruding semiconductor fin and a second portion of the dummy fin. The method further includes recessing a third portion of the first protruding semiconductor fin to form a recess, recessing an fourth portion of the dummy fin to reduce a height of the fourth portion of the dummy fin, and forming an epitaxy semiconductor region in the recess. The epitaxy semiconductor region is grown toward the dummy fin.

公开(公告)号：US11817503B2

公开(公告)日：2023-11-14

申请号：US17875152

申请日：2022-07-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L29/00 ,  H01L29/78 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L29/42356 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6656 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A device includes a substrate, a shallow trench isolation (STI) structure, an isolation structure, and a gate stack. The substrate has a semiconductor fin. The shallow trench isolation (STI) structure is over the substrate and laterally surrounding the semiconductor fin. The isolation structure is disposed on a top surface of the STI structure. The gate stack crosses the semiconductor fin, over the STI structure, and in contact with a sidewall the isolation structure, in which the gate stack includes a high-k dielectric layer extending from a sidewall of the semiconductor fin to the top surface of the STI structure and terminating prior to reaching the sidewall of the isolation structure, and the high-k dielectric layer is in contact with the top surface of the STI structure. The gate stack includes a gate electrode over the high-k dielectric layer and in contact with the sidewall of the isolation structure.