公开(公告)号：US10937704B1

公开(公告)日：2021-03-02

申请号：US16590177

申请日：2019-10-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Chiang ,  Chung-Wei Hsu ,  Lung-Kun Chu ,  Jia-Ni Yu ,  Chih-Hao Wang ,  Mao-Lin Huang

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/3213

Abstract: A method includes depositing a first conductive material on a first-type channel stack and a second-type channel stack, the first conductive material having a first workfunction, the first conductive material being formed between multiple layers of both the first-type channel stack and the second-type channel stack. The method further includes partially removing the first conductive material from the second-type channel stack such that the first conductive material remains between the multiple layers of both the first-type channel stack and the second-type channel stack and fully removing the first conductive material from the second-type channel stack. The method further includes depositing a second conductive material over both the first-type channel stack and the second-type channel stack such that the second conductive material covers both the first-type channel stack and the first conductive material in between the layers of the first-type channel stack, the second conductive material having a second workfunction that is different than the first workfunction.

公开(公告)号：US12237372B2

公开(公告)日：2025-02-25

申请号：US18295246

申请日：2023-04-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lung-Kun Chu ,  Jia-Ni Yu ,  Chung-Wei Hsu ,  Chih-Hao Wang ,  Kuo-Cheng Chiang ,  Kuan-Lun Cheng ,  Mao-Lin Huang

IPC: H01L29/06 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

Abstract: A device includes a substrate, and a first semiconductor channel over the substrate. The first semiconductor channel includes a first nanosheet of a first semiconductor material, a second nanosheet of a second semiconductor material in physical contact with a topside surface of the first nanosheet, and a third nanosheet of the second semiconductor material in physical contact with an underside surface of the first nanosheet. The first gate structure is over and laterally surrounding the first semiconductor channel, and in physical contact with the second nanosheet and the third nanosheet.

公开(公告)号：US12166100B2

公开(公告)日：2024-12-10

申请号：US18447006

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Wei Hsu ,  Kuo-Cheng Chiang ,  Lung-Kun Chu ,  Mao-Lin Huang ,  Jia-Ni Yu ,  Chih-Hao Wang

IPC: H01L29/51 ,  H01L21/02 ,  H01L29/06 ,  H01L29/66

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises first semiconductor layers and second semiconductor layers over a substrate, wherein the first semiconductor layers and the second semiconductor layers are separated and stacked up, and a thickness of each second semiconductor layer is less than a thickness of each first semiconductor layer; a first interfacial layer around each first semiconductor layer; a second interfacial layer around each second semiconductor layer; a first dipole gate dielectric layer around each first semiconductor layer and over the first interfacial layer; a second dipole gate dielectric layer around each second semiconductor layer and over the second interfacial layer; a first gate electrode around each first semiconductor layer and over the first dipole gate dielectric layer; and a second gate electrode around each second semiconductor layer and over the second dipole gate dielectric layer.

公开(公告)号：US20240371973A1

公开(公告)日：2024-11-07

申请号：US18773070

申请日：2024-07-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Peng-Soon Lim ,  Cheng-Lung Hung ,  Mao-Lin Huang ,  Weng Chang

IPC: H01L29/66 ,  H01L21/28 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78

Abstract: A method includes forming a dummy gate stack, forming a dielectric layer, with the dummy gate stack located in the dielectric layer, removing the dummy gate stack to form a opening in the dielectric layer, forming a metal layer extending into the opening, and etching back the metal layer. The remaining portions of the metal layer in the opening have edges lower than a top surface of the dielectric layer. A conductive layer is selectively deposited in the opening. The conductive layer is over the metal layer, and the metal layer and the conductive layer in combination form a replacement gate.

公开(公告)号：US12107131B2

公开(公告)日：2024-10-01

申请号：US18328520

申请日：2023-06-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Wei Hsu ,  Lung-Kun Chu ,  Mao-Lin Huang ,  Jia-Ni Yu ,  Kuo-Cheng Chiang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/417 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823475 ,  H01L29/42392 ,  H01L29/78696

Abstract: A semiconductor device includes a first interconnect structure and multiple channel layers stacked over the first interconnect structure. A bottommost one of the multiple channel layers is thinner than rest of the multiple channel layers. The semiconductor device further includes a gate stack wrapping around each of the channel layers except a bottommost one of the channel layers; a source/drain feature adjoining the channel layers; a first conductive via connecting the first interconnect structure to a bottom of the source/drain feature; and a dielectric feature under the bottommost one of the channel layers and directly contacting the first conductive via.

公开(公告)号：US12068393B2

公开(公告)日：2024-08-20

申请号：US17663979

申请日：2022-05-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Peng-Soon Lim ,  Cheng-Lung Hung ,  Mao-Lin Huang ,  Weng Chang

IPC: H01L29/66 ,  H01L21/28 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/06 ,  H01L29/51

CPC classification number: H01L29/66545 ,  H01L21/28026 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/66583 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/0673 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66439 ,  H01L29/665

Abstract: A method includes forming a dummy gate stack, forming a dielectric layer, with the dummy gate stack located in the dielectric layer, removing the dummy gate stack to form a opening in the dielectric layer, forming a metal layer extending into the opening, and etching back the metal layer. The remaining portions of the metal layer in the opening have edges lower than a top surface of the dielectric layer. A conductive layer is selectively deposited in the opening. The conductive layer is over the metal layer, and the metal layer and the conductive layer in combination form a replacement gate.

公开(公告)号：US20240234214A1

公开(公告)日：2024-07-11

申请号：US18615403

申请日：2024-03-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lung-Kun Chu ,  Mao-Lin Huang ,  Wei-Hao Wu ,  Kuo-Cheng Chiang

IPC: H01L21/8238 ,  H01L21/3213 ,  H01L27/092 ,  H01L29/40 ,  H01L29/423

CPC classification number: H01L21/823842 ,  H01L21/32134 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/401 ,  H01L29/42372

Abstract: A semiconductor device includes a semiconductor substrate; a plurality of channel regions, including a p-type channel region and an n-type channel region, disposed over the semiconductor substrate; and a gate structure. The gate structure includes a gate dielectric layer disposed over the plurality of channel regions and a work function metal (WFM) structure disposed over the gate dielectric layer. The WFM structure includes an n-type WFM layer over the n-type channel region and not over the p-type channel region and further includes a p-type WFM layer over both the n-type WFM layer and the p-type channel region. The gate structure further includes a fill metal layer disposed over the WFM structure and in direct contact with the p-type WFM layer.

公开(公告)号：US11915937B2

公开(公告)日：2024-02-27

申请号：US17378017

申请日：2021-07-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Mao-Lin Huang ,  Lung-Kun Chu ,  Huang-Lin Chao ,  Chi On Chui

IPC: H01L21/28 ,  H01L21/3115 ,  H01L29/66 ,  H01L29/40 ,  H01L27/092 ,  H01L29/423

CPC classification number: H01L21/28158 ,  H01L21/3115 ,  H01L27/092 ,  H01L29/401 ,  H01L29/66742 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/66439 ,  H01L29/66553

Abstract: A method includes forming a plurality of nanostructures over a substrate; etching the plurality of nanostructures to form recesses; forming source/drain regions in the recesses; removing first nanostructures of the plurality of nanostructures leaving second nanostructures of the plurality of nanostructures; depositing a gate dielectric over and around the second nanostructures; depositing a protective material over the gate dielectric; performing a fluorine treatment on the protective material; removing the protective material; depositing a first conductive material over the gate dielectric; and depositing a second conductive material over the first conductive material.

公开(公告)号：US11791218B2

公开(公告)日：2023-10-17

申请号：US16879613

申请日：2020-05-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lung-Kun Chu ,  Mao-Lin Huang ,  Chung-Wei Hsu ,  Jia-Ni Yu ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC: H01L21/8238 ,  H01L29/423 ,  H01L29/51 ,  H01L29/78 ,  H01L27/092 ,  H01L29/417 ,  H01L29/66 ,  H01L29/06 ,  H01L29/26 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L21/823821 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/26 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: A method includes providing a structure having a substrate, first and second channel layers over the substrate, and first and second gate dielectric layers over the first and the second channel layers respectively. The method further includes forming a first dipole pattern over the first gate dielectric layer, the first dipole pattern having a first dipole material that is of a first conductivity type; forming a second dipole pattern over the second gate dielectric layer, the second dipole pattern having a second dipole material that is of a second conductivity type opposite to the first conductivity type; and annealing the structure such that elements of the first dipole pattern are driven into the first gate dielectric layer and elements of the second dipole pattern are driven into the second gate dielectric layer.

公开(公告)号：US20230307552A1

公开(公告)日：2023-09-28

申请号：US18328946

申请日：2023-06-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mao-Lin Huang ,  Jia-Ni Yu ,  Lung-Kun Chu ,  Chung-Wei Hsu ,  Chih-Hao Wang ,  Kuo-Cheng Chiang ,  Kuan-Lun Cheng

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L29/78696 ,  H01L29/66742 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78684 ,  H01L21/02603 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02236 ,  H01L21/28185 ,  H01L21/823807 ,  H01L29/66545 ,  H01L29/66636 ,  H01L27/092

Abstract: A semiconductor device according to the present disclosure includes a fin structure over a substrate, a vertical stack of silicon nanostructures disposed over the fin structure, an isolation structure disposed around the fin structure, a germanium-containing interfacial layer wrapping around each of the vertical stack of silicon nanostructures, a gate dielectric layer wrapping around the germanium-containing interfacial layer, and a gate electrode layer wrapping around the gate dielectric layer.