公开(公告)号：US11756970B2

公开(公告)日：2023-09-12

申请号：US17328036

申请日：2021-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming Chyi Liu ,  Jiech-Fun Lu

IPC: H01L27/146 ,  H01L31/0232

CPC classification number: H01L27/14605 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14685 ,  H01L31/0232

Abstract: Various embodiments of the present disclosure are directed towards an image sensor. The image sensor comprises a plurality of photodetectors disposed within a substrate. A metal grid layer is disposed over the substrate. The metal grid layer comprises a metal grid structure overlying a central pixel region of the substrate. The metal grid layer continuously extends from the central pixel region to a peripheral pixel region of the substrate that laterally encloses the central pixel region. An upper metal structure is disposed over the metal grid layer. The upper metal structure overlies the peripheral pixel region. The upper metal structure is laterally offset from the metal grid structure. A lower surface of the upper metal structure is disposed vertically over an upper surface of the metal grid structure.

公开(公告)号：US20220285480A1

公开(公告)日：2022-09-08

申请号：US17361723

申请日：2021-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Alexander Kalnitsky ,  Ru-Liang Lee ,  Ming Chyi Liu ,  Sheng-Chan Li ,  Sheng-Chau Chen

IPC: H01L49/02

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a dielectric stack disposed over a substrate. The dielectric stack has a first plurality of layers interleaved between a second plurality of layers. The dielectric stack has one or more surfaces that define a plurality of indentations recessed into a side of the dielectric stack at different vertical heights corresponding to the second plurality of layers. A capacitor structure lines the one or more surfaces of the dielectric stack. The capacitor structure includes conductive electrodes separated by a capacitor dielectric.

公开(公告)号：US11417741B2

公开(公告)日：2022-08-16

申请号：US16953921

申请日：2020-11-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yong-Sheng Huang ,  Ming Chyi Liu

IPC: H01L29/792 ,  H01L29/423 ,  H01L21/28 ,  H01L27/1157 ,  H01L29/66

Abstract: The present disclosure relates to an integrated chip comprising a substrate having a first top surface disposed at a first height, a second top surface disposed at a second height that is less than the first height, and a connecting surface extending from the first top surface to the second top surface. A first source/drain region is disposed along the first top surface of the substrate. A second source/drain region is disposed along the second top surface of the substrate and is laterally separated from the first source/drain region by a channel region of the substrate. A gate structure is arranged between the first source/drain region and the second source/drain region. The gate structure extends from over the first top surface of the substrate to over the connecting surface of the substrate. The gate structure also extends below the first top surface of the substrate.

公开(公告)号：US11355596B2

公开(公告)日：2022-06-07

申请号：US17004365

申请日：2020-08-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming Chyi Liu

IPC: H01L29/40 ,  H01L21/768 ,  H01L29/66 ,  H01L29/78

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a gate dielectric, a gate electrode, a field plate dielectric layer, and a field plate. The gate dielectric layer is arranged over a substrate and between a source region and a drain region. The gate electrode is arranged over the gate dielectric layer. The field plate dielectric layer is arranged over the substrate and between the gate dielectric layer and the drain region. The field plate is arranged over the field plate dielectric layer and is spaced apart from the gate dielectric layer.

公开(公告)号：US20220165859A1

公开(公告)日：2022-05-26

申请号：US16953921

申请日：2020-11-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yong-Sheng Huang ,  Ming Chyi Liu

IPC: H01L29/423 ,  H01L21/28 ,  H01L29/66 ,  H01L29/792 ,  H01L27/1157

Abstract: The present disclosure relates to an integrated chip comprising a substrate having a first top surface disposed at a first height, a second top surface disposed at a second height that is less than the first height, and a connecting surface extending from the first top surface to the second top surface. A first source/drain region is disposed along the first top surface of the substrate. A second source/drain region is disposed along the second top surface of the substrate and is laterally separated from the first source/drain region by a channel region of the substrate. A gate structure is arranged between the first source/drain region and the second source/drain region. The gate structure extends from over the first top surface of the substrate to over the connecting surface of the substrate. The gate structure also extends below the first top surface of the substrate.

公开(公告)号：US11329128B2

公开(公告)日：2022-05-10

申请号：US16921075

申请日：2020-07-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jhih-Bin Chen ,  Ming Chyi Liu

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/08

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a source region disposed within a substrate and a drain region disposed within the substrate. The drain region is separated from the source region along a first direction. A drift region is disposed within the substrate between the source region and the drain region, and a plurality of isolation structures are disposed within the drift region. A gate electrode is disposed within the substrate. The gate electrode has a base region disposed between the source region and the drift region and a plurality of gate extensions extending outward from a sidewall of the base region to over the plurality of isolation structures.

公开(公告)号：US11158797B2

公开(公告)日：2021-10-26

申请号：US16009327

申请日：2018-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming Chyi Liu ,  Yuan-Tai Tseng ,  Chern-Yow Hsu ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC: H01L45/00 ,  H01L27/24

Abstract: The present disclosure relates to a resistive random access memory (RRAM) device architecture, that includes a thin single layer of a conductive etch-stop layer between a lower metal interconnect and a bottom electrode of an RRAM cell. The conductive etch-stop layer provides simplicity in structure and the etch-selectivity of this layer provides protection to the underlying layers. The conductive etch stop layer can be etched using a dry or wet etch to land on the lower metal interconnect. In instances where the lower metal interconnect is copper, etching the conductive etch stop layer to expose the copper does not produce as much non-volatile copper etching by-products as in traditional methods. Compared to traditional methods, some embodiments of the disclosed techniques reduce the number of mask step and also reduce chemical mechanical polishing during the formation of the bottom electrode.

公开(公告)号：US11107825B2

公开(公告)日：2021-08-31

申请号：US16909066

申请日：2020-06-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Shu Huang ,  Ming Chyi Liu

IPC: G11C16/04 ,  H01L27/11556 ,  H01L29/423 ,  H01L27/1158 ,  H01L29/66

Abstract: The present disclosure relates to a flash memory structure. The flash memory structure includes a first doped region and a second doped region disposed within a substrate. A select gate is disposed over the substrate between the first doped region and the second doped region. A floating gate is disposed over the substrate between the select gate and the first doped region, and a control gate is over the floating gate. The floating gate extends along multiple surfaces of the substrate.

公开(公告)号：US11069873B2

公开(公告)日：2021-07-20

申请号：US16601712

申请日：2019-10-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung-Chang Chang ,  Ming Chyi Liu

IPC: H01L51/52 ,  H01L27/32 ,  H01L51/56

Abstract: In some embodiments, the present disclosure relates to a display device that includes an isolation structure disposed over a reflector electrode, a transparent electrode disposed over the isolation structure, an optical emitter structure disposed over the transparent electrode, and a via structure. The via structure extends from the transparent electrode at a top surface of the isolation structure to a top surface of the reflector electrode. The via structure includes a center horizontal segment that contacts the top surface of the reflector electrode, a sidewall vertical segment that contacts an inner sidewall of the isolation structure, and an upper horizontal segment that is connected to the center horizontal segment by the sidewall vertical segment. The upper horizontal segment is thicker than the center horizontal segment.

公开(公告)号：US20210184005A1

公开(公告)日：2021-06-17

申请号：US17004365

申请日：2020-08-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming Chyi Liu

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a gate dielectric, a gate electrode, a field plate dielectric layer, and a field plate. The gate dielectric layer is arranged over a substrate and between a source region and a drain region. The gate electrode is arranged over the gate dielectric layer. The field plate dielectric layer is arranged over the substrate and between the gate dielectric layer and the drain region. The field plate is arranged over the field plate dielectric layer and is spaced apart from the gate dielectric layer