公开(公告)号：US08928038B2

公开(公告)日：2015-01-06

申请号：US14117763

申请日：2012-05-15

申请人： Yasuhiro Okamoto ,  Yuji Ando ,  Tatsuo Nakayama ,  Takashi Inoue ,  Kazuki Ota

发明人： Yasuhiro Okamoto ,  Yuji Ando ,  Tatsuo Nakayama ,  Takashi Inoue ,  Kazuki Ota

IPC分类号： H01L29/66 ,  H01L29/778 ,  H01L29/205 ,  H01L29/20 ,  H01L29/423 ,  H01L29/51

CPC分类号： H01L29/7787 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/4236 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7786

摘要： A field effect transistor includes a substrate and a semiconductor layer provided on the substrate, wherein the semiconductor layer includes a lower barrier layer provided on the substrate, Ga-face grown, lattice relaxed, and having a composition In1-zAlzN (0≦z≦1), a channel layer having a composition of: AlxGa1-xN (0≦x≦1) or InyGa1-yN (0≦y≦1). Or GaN provided on and lattice-matched to the lower barrier layer, a source electrode and a drain electrode having ohmic contact to an upper part of the semiconductor layers, disposed spaced to each other, and a gate electrode arranged via a gate insulating film in a region lying between the source electrode and the drain electrode.

摘要翻译： 场效应晶体管包括衬底和设置在衬底上的半导体层，其中半导体层包括设置在衬底上的下阻挡层，生长Ga面，晶格弛豫并具有组成In 1-z Al z N（0＆nl; z＆nl E; 1），具有以下组成的沟道层：Al x Ga 1-x N（0＆amp; nlE; x＆nlE; 1）或In y Ga 1-y N（0＆nlE; y＆nlE; 1）。 或提供在栅极绝缘膜上并与栅极绝缘膜配置的栅电极，栅极配置在栅极绝缘膜上，栅电极配置在栅极绝缘膜上， 位于源电极和漏电极之间的区域。

公开(公告)号：US20130105811A1

公开(公告)日：2013-05-02

申请号：US13637555

申请日：2010-12-15

申请人： Yuji Ando ,  Takashi Inoue ,  Kazuki Ota ,  Yasuhiro Okamoto ,  Tatsuo Nakayama ,  Kazuomi Endo

发明人： Yuji Ando ,  Takashi Inoue ,  Kazuki Ota ,  Yasuhiro Okamoto ,  Tatsuo Nakayama ,  Kazuomi Endo

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/20

CPC分类号： H01L29/78 ,  H01L21/8252 ,  H01L29/2003 ,  H01L29/4232 ,  H01L29/66477 ,  H01L29/7785 ,  H01L29/7787

摘要： The present invention provides a field effect transistor which can achieve both of a high threshold voltage and a low on-state resistance, a method for producing the same, and an electronic device. In the field effect transistor, each of a buffer layer 112, a channel layer 113, a barrier layer 114, and a spacer layer 115 is formed of a group-III nitride semiconductor, and each of the upper surfaces thereof is a group-III atomic plane that is perpendicular to a (0001) crystal axis. The lattice-relaxed buffer layer 112, the channel layer 113 having a compressive strain, and the barrier layer 114 having a tensile strain, and the spacer layer 115 having a compressive strain are laminated on a substrate 100 in this order. The gate insulating film 14 is arranged on the spacer layer 115. The gate electrode 15 is arranged on the gate insulating film 14. The source electrode 161 and the drain electrode 162 are electrically connected to the channel layer 113 directly or via another component.

摘要翻译： 本发明提供了能够实现高阈值电压和低通态电阻两者的场效应晶体管，其制造方法和电子器件。 在场效应晶体管中，由III族氮化物半导体形成缓冲层112，沟道层113，势垒层114和间隔层115，其上表面分别为III族 原子平面垂直于（0001）晶轴。 栅格弛豫缓冲层112，具有压缩应变的沟道层113和具有拉伸应变的阻挡层114以及具有压缩应变的间隔层115以此顺序层压在基板100上。 栅极绝缘膜14布置在间隔层115上。栅电极15布置在栅极绝缘膜14上。源极161和漏极162直接或经由另一个部件电连接到沟道层113。

公开(公告)号：US08921894B2

公开(公告)日：2014-12-30

申请号：US13637555

申请日：2010-12-15

申请人： Yuji Ando ,  Takashi Inoue ,  Kazuki Ota ,  Yasuhiro Okamoto ,  Tatsuo Nakayama ,  Kazuomi Endo

发明人： Yuji Ando ,  Takashi Inoue ,  Kazuki Ota ,  Yasuhiro Okamoto ,  Tatsuo Nakayama ,  Kazuomi Endo

IPC分类号： H01L29/778 ,  H01L21/8252 ,  H01L29/78 ,  H01L29/20 ,  H01L29/423 ,  H01L29/66

CPC分类号： H01L29/78 ,  H01L21/8252 ,  H01L29/2003 ,  H01L29/4232 ,  H01L29/66477 ,  H01L29/7785 ,  H01L29/7787

摘要： The present invention provides a field effect transistor which can achieve both of a high threshold voltage and a low on-state resistance, a method for producing the same, and an electronic device. In the field effect transistor, each of a buffer layer 112, a channel layer 113, a barrier layer 114, and a spacer layer 115 is formed of a group-III nitride semiconductor, and each of the upper surfaces thereof is a group-III atomic plane that is perpendicular to a (0001) crystal axis. The lattice-relaxed buffer layer 112, the channel layer 113 having a compressive strain, and the barrier layer 114 having a tensile strain, and the spacer layer 115 having a compressive strain are laminated on a substrate 100 in this order. The gate insulating film 14 is arranged on the spacer layer 115. The gate electrode 15 is arranged on the gate insulating film 14. The source electrode 161 and the drain electrode 162 are electrically connected to the channel layer 113 directly or via another component.

摘要翻译： 本发明提供了能够实现高阈值电压和低通态电阻两者的场效应晶体管，其制造方法和电子器件。 在场效应晶体管中，由III族氮化物半导体形成缓冲层112，沟道层113，势垒层114和间隔层115，其上表面为III族 原子平面垂直于（0001）晶轴。 栅格弛豫缓冲层112，具有压缩应变的沟道层113和具有拉伸应变的阻挡层114以及具有压缩应变的间隔层115以此顺序层压在基板100上。 栅极绝缘膜14布置在间隔层115上。栅电极15布置在栅极绝缘膜14上。源极161和漏极162直接或经由另一个部件电连接到沟道层113。

公开(公告)号：US20130099245A1

公开(公告)日：2013-04-25

申请号：US13637316

申请日：2010-12-15

申请人： Yuji Ando ,  Takashi Inoue ,  Kazuki Ota ,  Yasuhiro Okamoto ,  Tatsuo Nakayama ,  Kazuomi Endo

发明人： Yuji Ando ,  Takashi Inoue ,  Kazuki Ota ,  Yasuhiro Okamoto ,  Tatsuo Nakayama ,  Kazuomi Endo

IPC分类号： H01L29/205 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/205 ,  H01L29/2003 ,  H01L29/4232 ,  H01L29/66431 ,  H01L29/7785 ,  H01L29/7787 ,  H01L29/78

摘要： The present invention provides a field effect transistor which can achieve both of a high threshold voltage and a low on-state resistance, a method for producing the same, and an electronic device. In the field effect transistor, each of a buffer layer 112, a channel layer 113, a barrier layer 114, and a spacer layer 115 is formed of a group-III nitride semiconductor, and each of the upper surfaces thereof is a group-III atomic plane that is perpendicular to a (0001) crystal axis. The lattice-relaxed buffer layer 112, the lattice-relaxed channel layer 113, and the barrier layer 114 having a tensile strain, and the spacer layer 115 are laminated on a substrate 100 in this order. The gate insulating film 14 is arranged on the spacer layer 115. The gate electrode 15 is arranged on the gate insulating film 14. The source electrode 161 and the drain electrode 162 are electrically connected to the channel layer 113 directly or via another component.

摘要翻译： 本发明提供了能够实现高阈值电压和低通态电阻两者的场效应晶体管，其制造方法和电子器件。 在场效应晶体管中，由III族氮化物半导体形成缓冲层112，沟道层113，势垒层114和间隔层115，其上表面为III族 原子平面垂直于（0001）晶轴。 晶格弛豫缓冲层112，晶格松弛沟道层113和具有拉伸应变的势垒层114和间隔层115依次层压在基板100上。 栅极绝缘膜14布置在间隔层115上。栅电极15布置在栅极绝缘膜14上。源极161和漏极162直接或经由另一个部件电连接到沟道层113。

公开(公告)号：US5373168A

公开(公告)日：1994-12-13

申请号：US988407

申请日：1992-12-07

申请人： Yuji Ando ,  Kazuhiko Onda ,  Masaaki Kuzuhara

发明人： Yuji Ando ,  Kazuhiko Onda ,  Masaaki Kuzuhara

IPC分类号： H01L29/812 ,  H01L21/338 ,  H01L29/10 ,  H01L29/778 ,  H01L29/80 ,  H01L29/161 ,  H01L29/205 ,  H01L29/227

CPC分类号： H01L29/7783 ,  H01L29/1029

摘要： The invention provides a compound semiconductor multilayer structure having a two-dimensional electron gas, which is applicable to field effect transistors. A ternary compound InGaAs planar channel layer serving as a quantum well has a variation of an In (indium) fraction in a perpendicular direction to a heterojunction interface. The variation has a step-graded profile with taking a maximum value at or in the vicinity of a portion where the two-dimensional electron gas takes a maximum density. Such quantum well has most large depth at a portion except for adjacent portions to the heterojunction interfaces. Such multilayer structure provides a great electron mobility and a strong electron confinement to major electrons at a high electron density portion. Such multilayer structure provides the large effective electron mobility and the large sheet electron density to the two-dimensional electron gas without a gain of the average of the In (indium) fractions, thereby suppressing the enlargement of the lattice mismatch which causes misfit dislocations in crystals.

摘要翻译： 本发明提供一种可应用于场效应晶体管的具有二维电子气的化合物半导体多层结构。 用作量子阱的三元化合物InGaAs平面沟道层在与异质结界面垂直的方向上具有In（铟）分数的变化。 该变化具有在二维电子气具有最大密度的部分处或附近具有最大值的阶梯分布。 这样的量子阱在除异质结界面的相邻部分之外的部分具有最大的深度。 这种多层结构在高电子密度部分提供了大的电子迁移率和对主要电子的强电子约束。 这种多层结构为二维电子气体提供了大的有效电子迁移率和大的片状电子密度，而不增加In（铟）级分的平均值，从而抑制晶格失配的扩大，这导致晶体失配位错 。

公开(公告)号：US07802564B2

公开(公告)日：2010-09-28

申请号：US10583974

申请日：2004-12-08

申请人： Yuji Ando ,  Kazuyuki Matsubayashi ,  Shinya Ueda

发明人： Yuji Ando ,  Kazuyuki Matsubayashi ,  Shinya Ueda

IPC分类号： A21B1/08 ,  A21B1/22

CPC分类号： F24C15/327

摘要： In a ceiling part of a heating chamber, a sub-cavity is provided in which a steam-heating heater is housed. Steam generated by a steam generating device is heated by the steam-heating heater inside the sub-cavity to be brought into an overheated state, and is then jetted out through upper jet holes provided in the ceiling part of the heating chamber and through side jet holes provided in lower parts of the side walls of the heating chamber at both sides thereof. Food is supported on a rack to be in a state floating above the floor surface of the heating chamber, and, through the side jet holes, steam is jetted toward under the food.

摘要翻译： 在加热室的天花板部分中，设置有容纳蒸汽加热加热器的子腔。 由蒸汽发生装置产生的蒸汽由子腔内的蒸汽加热加热器加热，使其处于过热状态，然后通过设置在加热室的顶部的上部喷射孔并通过侧面喷射 设置在加热室侧壁的两侧的孔。 食物被支撑在架子上，处于浮在加热室的地板表面上方的状态，并且通过侧面喷射孔将蒸汽朝向食物下方喷射。

公开(公告)号：US07801214B2

公开(公告)日：2010-09-21

申请号：US10989709

申请日：2004-11-16

申请人： Hideyuki Ichihashi ,  Yuji Ando

发明人： Hideyuki Ichihashi ,  Yuji Ando

IPC分类号： H04B1/66

CPC分类号： H04N19/198 ,  H04N19/124 ,  H04N19/14 ,  H04N19/142 ,  H04N19/15 ,  H04N19/152 ,  H04N19/164 ,  H04N19/172 ,  H04N19/176 ,  H04N19/196 ,  H04N19/37 ,  H04N19/61

摘要： A data processing apparatus able to generate encoded data able to give a high quality decoded image, wherein a Q-calculation circuit specifies a bit rate by which the encoded data is decoded at the time of decoding based on encoded data, then the Q-calculation circuit controls quantization scales of a quantization circuit based on the specified bit rate.

摘要翻译： 一种数据处理装置，其能够生成能够提供高质量解码图像的编码数据，其中Q计算电路基于编码数据指定在解码时对编码数据进行解码的比特率，然后进行Q-计算 电路基于指定的比特率控制量化电路的量化尺度。

公开(公告)号：US20080223352A1

公开(公告)日：2008-09-18

申请号：US10583974

申请日：2004-12-08

申请人： Yuji Ando ,  Kazuyuki Matsubayashi ,  Shinya Ueda

发明人： Yuji Ando ,  Kazuyuki Matsubayashi ,  Shinya Ueda

IPC分类号： F24C1/00

CPC分类号： F24C15/327

摘要： In a ceiling part of a heating chamber, a sub-cavity is provided in which a steam-heating heater is housed. Steam generated by a steam generating device is heated by the steam-heating heater inside the sub-cavity to be brought into an overheated state, and is then jetted out through upper jet holes provided in the ceiling part of the heating chamber and through side jet holes provided in lower parts of the side walls of the heating chamber at both sides thereof. Food is supported on a rack to be in a state floating above the floor surface of the heating chamber, and, through the side jet holes, steam is jetted toward under the food.

摘要翻译： 在加热室的天花板部分中，设置有容纳蒸汽加热加热器的子腔。 由蒸汽发生装置产生的蒸汽由子腔内的蒸汽加热加热器加热，使其处于过热状态，然后通过设置在加热室的顶部的上部喷射孔并通过侧面喷射 设置在加热室侧壁的两侧的孔。 食物被支撑在架子上，处于浮在加热室的地板表面上方的状态，并且通过侧面喷射孔将蒸汽朝向食物下方喷射。

公开(公告)号：US06849164B2

公开(公告)日：2005-02-01

申请号：US10141781

申请日：2002-05-10

申请人： Toyoji Ataka ,  Yuji Ando ,  Satoru Nakamura ,  Katsuya Masuda ,  Manabu Shimosato

发明人： Toyoji Ataka ,  Yuji Ando ,  Satoru Nakamura ,  Katsuya Masuda ,  Manabu Shimosato

IPC分类号： G11B5/65 ,  G11B5/73 ,  G11B5/738 ,  G11B5/84 ,  G11B5/851 ,  C23C14/32 ,  C23C16/00

CPC分类号： G11B5/732 ,  G11B5/7325 ,  G11B5/8404

摘要： A magnetic recording medium and method of manufacturing the same including directly texturing a surface of a non-magnetic substrate made of a glass material to form circular concentric grooves thereon, forming a seed layer on the non-magnetic substrate, forming an under layer on the seed layer, forming a magnetic layer on the under layer, and forming a protective layer on the magnetic layer. A ratio of an in-plane remanent magnetization in a circumferential direction of the magnetic recording medium to an in-plane remanent magnetization in a radial direction of the magnetic recording medium is equal to or greater than 1.05.

摘要翻译： 一种磁记录介质及其制造方法，包括直接对由玻璃材料制成的非磁性基板的表面进行纹理化以在其上形成圆形同心凹槽，在非磁性基板上形成晶种层，在非磁性基板上形成下层 种子层，在下层上形成磁性层，在该磁性层上形成保护层。 磁记录介质的圆周方向上的面内剩余磁化强度与磁记录介质的径向方向上的平面内剩余磁化强度之比等于或大于1.05。

公开(公告)号：US06489426B1

公开(公告)日：2002-12-03

申请号：US09643742

申请日：2000-08-23

申请人： Naoshi Kawamoto ,  Yasuhiro Shiraishi ,  Atsuko Sawai ,  Yuji Ando ,  Shinji Nakata ,  Hisanobu Minamizawa ,  Ichiro Sakabe ,  Katsuhiko Ohno

发明人： Naoshi Kawamoto ,  Yasuhiro Shiraishi ,  Atsuko Sawai ,  Yuji Ando ,  Shinji Nakata ,  Hisanobu Minamizawa ,  Ichiro Sakabe ,  Katsuhiko Ohno

IPC分类号： C08F11006

CPC分类号： C08J5/18 ,  C08F10/06 ,  C08F110/06 ,  C08F210/06 ,  C08J2323/10 ,  C08F2500/12 ,  C08F2500/26 ,  C08F210/16

摘要： Propylene homopolymers or propylene-olefin copolymers, having at least one olefin selected from ethylene and &agr;-olefins having 4 or more carbon atoms where the propylene content in this copolymer is 98% by weight or more, are provided that are suitable for producing films with excellent antistatic performance, high rigidity and metallizability.

摘要翻译： 丙烯均聚物或丙烯 - 烯烃共聚物，其具有选自乙烯和具有4个或更多个碳原子的α-烯烃的至少一种烯烃，其中该共聚物中的丙烯含量为98重量％以上，适用于制备具有 优异的抗静电性能，高刚性和镀层性。