公开(公告)号：US07638990B1

公开(公告)日：2009-12-29

申请号：US11754295

申请日：2007-05-27

Applicant: Sergey Shumarayev ,  Simardeep Maangat

Inventor： Sergey Shumarayev ,  Simardeep Maangat

IPC: G05F1/40 ,  G05F1/56

CPC classification number: G05F1/56

Abstract: A power management system on an integrated circuit can include a first switch and a second switch. A regulator circuit provides current from a first supply voltage to a circuit block when the first switch is closed. The second switch provides current from a second supply voltage to the circuit block when the second switch is closed.

Abstract translation: 集成电路上的电源管理系统可以包括第一开关和第二开关。 当第一开关闭合时，调节器电路将电流从第一电源电压提供给电路块。 当第二开关闭合时，第二开关将电流从第二电源电压提供给电路块。

公开(公告)号：US07589651B1

公开(公告)日：2009-09-15

申请号：US11467332

申请日：2006-08-25

Applicant: Sergey Shumarayev ,  Rakesh H. Patel ,  Wilson Wong

Inventor： Sergey Shumarayev ,  Rakesh H. Patel ,  Wilson Wong

IPC: H03M1/00

CPC classification number: H03K19/17744 ,  H03K19/17732

Abstract: A serial interface for a programmable logic device (PLD) uses an analog-to-digital converter (ADC) in place of conventional signal detect and receiver detect circuitry. A separate ADC can be used in each receiver and each transmitter in each serial interface on the PLD. Alternatively, time division multiplexing can be used to allow the receiver and transmitter in each receiver/transmitter pair, or even multiple receiver/transmitter pairs, to share a single ADC. When none of the receiver/transmitter pairs associated with a particular ADC is being used, the ADC can be accessed for use simply as an ADC.

Abstract translation: 用于可编程逻辑器件（PLD）的串行接口使用模数转换器（ADC）来代替传统的信号检测和接收器检测电路。 在PLD的每个串行接口中的每个接收器和每个发射器中可以使用单独的ADC。 或者，可以使用时分复用来允许每个接收机/发射机对中的接收机和发射机，或甚至多个接收机/发射机对共享单个ADC。 当没有使用与特定ADC相关联的接收器/发送器对时，ADC可以被简单地用作ADC。

公开(公告)号：US07576570B1

公开(公告)日：2009-08-18

申请号：US11508607

申请日：2006-08-22

Applicant: Wilson Wong ,  Sergey Shumarayev ,  Simardeep Maangat ,  Thungoc M. Tran ,  Tim Tri Hoang

Inventor： Wilson Wong ,  Sergey Shumarayev ,  Simardeep Maangat ,  Thungoc M. Tran ,  Tim Tri Hoang

IPC: H03K5/153

CPC classification number: H03K5/153 ,  H03K5/24

Abstract: Precision amplitude detection circuitry without pattern dependencies is provided that includes rectifier circuitry to output a rectified voltage signal and delay circuitry to send one or more delayed or phase-shifted versions of a differential signal input to the rectifier circuitry. The delayed versions of the differential signal input may be delayed in order to reduce or eliminate the dips in the input seen by the rectifier. This may help correct for low rectified voltage levels. The signal amplitude detection circuitry of the present invention may be incorporated on the input pin of any programmable logic resource and may be included in communication circuitry of a PLD. The precision amplitude detection circuitry may operate in the Gbps (gigabit per second) range.

Abstract translation: 提供了没有图形相关性的精密幅度检测电路，其包括整流电路，用于输出整流电压信号和延迟电路，以将一个或多个差分信号输入的延迟或相移版本发送到整流器电路。 可以延迟差分信号输入的延迟版本，以便减少或消除由整流器看到的输入中的下降。 这可能有助于校正低整流电压电平。 本发明的信号幅度检测电路可以结合在任何可编程逻辑资源的输入引脚上，并且可以被包括在PLD的通信电路中。 精度幅度检测电路可以以Gbps（千兆位/秒）范围工作。

公开(公告)号：US20090161738A1

公开(公告)日：2009-06-25

申请号：US12283652

申请日：2008-09-15

Applicant: Neville Carvalho ,  Allan Thomas Davidson ,  Andy Turudic ,  Bruce B. Pedersen ,  David W. Mendel ,  Kalyan Kankipati ,  Michael Menghui Zheng ,  Sergey Shumarayev ,  Seungmyon Park ,  Tim Tri Hoang ,  Kumara Tharmalingam

Inventor： Neville Carvalho ,  Allan Thomas Davidson ,  Andy Turudic ,  Bruce B. Pedersen ,  David W. Mendel ,  Kalyan Kankipati ,  Michael Menghui Zheng ,  Sergey Shumarayev ,  Seungmyon Park ,  Tim Tri Hoang ,  Kumara Tharmalingam

IPC: H04L7/00 ,  H04B1/38

CPC classification number: H04L25/14

Abstract: A transceiver system with reduced latency uncertainty is described. In one implementation, the transceiver system has a word aligner latency uncertainty of zero. In another implementation, the transceiver system has a receiver-to-transmitter transfer latency uncertainty of zero. In yet another implementation, the transceiver system has a word aligner latency uncertainty of zero and a receiver-to-transmitter transfer latency uncertainty of zero. In one specific implementation, the receiver-to-transmitter transfer latency uncertainty is eliminated by using the transmitter parallel clock as a feedback signal in the transmitter phase locked loop (PLL). In one implementation, this is achieved by optionally making the transmitter divider, which generates the transmitter parallel clock, part of the feedback path of the transmitter PLL. In one implementation, the word aligner latency uncertainty is eliminated by using a bit slipper to slip bits in such a way so that the total delay due to the word alignment and bit slipping is constant for all phases of the recovered clock. This allows for having a fixed and known latency between the receipt and transmission of bits for all phases of parallelization by the deserializer. In one specific implementation, the total delay due to the bit shifting by the word aligner and the bit slipping by the bit slipper is zero since the bit slipper slips bits so as to compensate for the bit shifting that was performed by the word aligner.

Abstract translation: 描述了具有降低的等待时间不确定性的收发机系统。 在一个实现中，收发器系统具有字对齐器等待时间不确定度为零。 在另一个实现中，收发器系统具有接收器到发射器的传输等待时间不确定度为零。 在另一个实现中，收发器系统具有字对齐器延迟不确定度为零和接收器到发射器的传输等待时间不确定度为零。 在一个具体实现中，通过在发射机锁相环（PLL）中使用发射机并行时钟作为反馈信号来消除接收机到发射机的传输等待时间不确定性。 在一个实现中，这通过可选地使发射机分频器（其产生发射机并行时钟）作为发射机PLL的反馈路径的一部分来实现。 在一个实施方案中，通过使用位拖动器以这样的方式滑动位来消除字对齐器延迟不确定性，使得由于字对齐和位滑动引起的总延迟对于恢复时钟的所有阶段是恒定的。 这允许在由解串器的并行化的所有阶段的位的接收和传输之间具有固定和已知的等待时间。 在一个具体实现中，由于位对准器的位移和由位拖动器的位滑动导致的总延迟为零，因为位拖动器滑动位，以补偿由字对准器执行的位移。

公开(公告)号：US20080246516A1

公开(公告)日：2008-10-09

申请号：US11696575

申请日：2007-04-04

Applicant: Tim Tri Hoang ,  Sergey Shumarayev ,  Wanli Chang

Inventor： Tim Tri Hoang ,  Sergey Shumarayev ,  Wanli Chang

IPC: H03D13/00

CPC classification number: H03D13/004

Abstract: A phase frequency detector compares a reference clock signal to a feedback clock signal to generate pulses in one or more output signals. The one or more output signals have a minimum pulse width. The phase frequency detector has a temperature sensing circuit. The phase frequency detector adjusts the minimum pulse width of the one or more output signals using the temperature sensing circuit to compensate for variations in the temperature of the phase frequency detector.

Abstract translation: 相位频率检测器将参考时钟信号与反馈时钟信号进行比较，以在一个或多个输出信号中产生脉冲。 一个或多个输出信号具有最小的脉冲宽度。 相位频率检测器具有温度检测电路。 相位频率检测器使用温度检测电路调节一个或多个输出信号的最小脉冲宽度，以补偿相位频率检测器的温度变化。

公开(公告)号：US07411464B1

公开(公告)日：2008-08-12

申请号：US11430469

申请日：2006-05-08

Applicant: Tim T Hoang ,  Sergey Shumarayev

Inventor： Tim T Hoang ,  Sergey Shumarayev

IPC: H03B5/24 ,  H03L1/00 ,  H03L7/099

CPC classification number: H03K5/1565 ,  H03K3/0315 ,  H03L7/18

Abstract: An oscillator circuit can generate a periodic signal, and a frequency adjustment circuit can adjust the frequency of the periodic signal. The periodic signal may include phase jitter. In one aspect of the invention, the phase jitter may be mitigated by connecting other circuitry to the oscillator circuit and allowing the other circuitry to draw current. In one embodiment, the other circuitry is connected in parallel with the oscillator circuit. In one embodiment, the other circuitry is configured to draw greater current to mitigate more phase jitter and to draw less current to mitigate less phase jitter. In one embodiment, a greater portion of the other circuitry is connected to the oscillator circuit for higher frequencies and a lesser portion of the other circuitry is connected to the oscillator circuit for lower frequencies.

Abstract translation: 振荡器电路可以产生周期信号，并且频率调节电路可以调节周期信号的频率。 周期信号可能包括相位抖动。 在本发明的一个方面，通过将其它电路连接到振荡器电路并允许其它电路抽取电流可以减轻相位抖动。 在一个实施例中，另一个电路与振荡器电路并联连接。 在一个实施例中，另一个电路被配置为绘制更大的电流以减轻更多的相位抖动并绘制更少的电流以减轻较少的相位抖动。 在一个实施例中，其他电路的较大部分连接到振荡器电路用于较高频率，而另一电路的较小部分连接到用于较低频率的振荡器电路。

公开(公告)号：US07355462B1

公开(公告)日：2008-04-08

申请号：US11456484

申请日：2006-07-10

Applicant: Wilson Wong ,  Rakesh H. Patel ,  Sergey Shumarayev

Inventor： Wilson Wong ,  Rakesh H. Patel ,  Sergey Shumarayev

IPC: H03L7/06

CPC classification number: H03L7/089 ,  H03L7/093 ,  H03L7/18

Abstract: A digital controller for a voltage controlled oscillator (VCO) is provided within a phase lock loop (PLL). The digital controller includes a digital filter having first and second inputs for receiving upward and downward adjustment signals, respectively. The digital filter generates an increment signal and a decrement signal in response to the upward and downward adjustment signals, respectively. The digital controller includes a digital counter having first and second inputs for receiving the increment and decrement signals, respectively. The digital counter generates a multi-bit output signal that represents a running sum of the increment and decrement signals. The digital controller further includes a digital-to-analog converter (DAC) having an input for receiving the running sum output signal generated by the digital counter. The DAC is defined to generate a control voltage for the VCO in response to receipt of the running sum output signal from the digital counter.

Abstract translation: 在锁相环（PLL）内提供压控振荡器（VCO）的数字控制器。 数字控制器包括具有分别用于接收上下调节信号的第一和第二输入的数字滤波器。 数字滤波器分别响应于上下调节信号产生增量信号和减量信号。 数字控制器包括一个数字计数器，它具有分别用于接收增量和减量信号的第一和第二输入端。 数字计数器产生一个多位输出信号，表示增量和减量信号的运行和。 数字控制器还包括具有用于接收由数字计数器产生的运行和输出信号的输入的数模转换器（DAC）。 DAC被定义为响应于来自数字计数器的运行和输出信号的接收而产生用于VCO的控制电压。

公开(公告)号：US20070127616A1

公开(公告)日：2007-06-07

申请号：US11292565

申请日：2005-12-02

Applicant: Sergey Shumarayev ,  Rakesh Patel

Inventor： Sergey Shumarayev ,  Rakesh Patel

IPC: H03D3/24

CPC classification number: H03K19/17744 ,  H03L7/0995

Abstract: A field-programmable gate array (“FPGA”) may include data receiver and/or transmitter circuitry that is adapted to receive and/or transmit data at any frequency(ies) or data rate(s) in a wide range of possible frequencies or data rates. Phase-locked loop (PLL) circuitry may be needed for operation of such receiver and/or transmitter circuitry. For satisfactory operation over the wide frequency range, multiple PLL circuits are provided. One of these PLL circuits may be capable of operating over the entire frequency range, possibly with better jitter performance in some portions of the range than in other portions of the range. One or more other PLL circuits may be provided that are focused on particular parts of the broad range, especially where the jitter performance of the first-mentioned PLL may not be adequate to meet some possible needs.

Abstract translation: 现场可编程门阵列（“FPGA”）可以包括数据接收器和/或发射机电路，其适于在宽范围的可能频率中以任何频率或数据速率接收和/或发射数据，或 数据速率。 可能需要锁相环（PLL）电路来操作这种接收器和/或发射器电路。 为了在宽频率范围内的令人满意的操作，提供了多个PLL电路。 这些PLL电路中的一个可能能够在整个频率范围内运行，可能在该范围的某些部分中具有比该范围的其他部分更好的抖动性能。 可以提供一个或多个其他PLL电路，其集中在宽范围的特定部分上，特别是在首先提到的PLL的抖动性能可能不足以满足一些可能需要的地方。

公开(公告)号：US20070030184A1

公开(公告)日：2007-02-08

申请号：US11364589

申请日：2006-02-27

Applicant: Toan Thanh Nguyen ,  Thungoc Tran ,  Sergey Shumarayev ,  Arch Zaliznyak ,  Shoujun Wang ,  Ramanand Venkata ,  Chong Lee

Inventor： Toan Thanh Nguyen ,  Thungoc Tran ,  Sergey Shumarayev ,  Arch Zaliznyak ,  Shoujun Wang ,  Ramanand Venkata ,  Chong Lee

IPC: H03M9/00

CPC classification number: H03K19/00 ,  H03K19/17744 ,  H03M9/00 ,  H04L1/243 ,  H04L7/0008 ,  H04L7/033 ,  H04L25/0266

Abstract: Serializer circuitry for high-speed serial data transmitter circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting parallel data having any of several data widths to serial data. The circuitry can also operate at any frequency in a wide range of frequencies, and can make use of reference clock signals having any of several relationships to the parallel data rate and/or the serial data rate. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).

Abstract translation: 用于可编程逻辑器件（“PLD”）等上的高速串行数据发射器电路的串行器电路包括用于将具有若干数据宽度中的任一个的并行数据转换为串行数据的电路。 电路还可以在宽频率范围内的任何频率下操作，并且可以利用具有与并行数据速率和/或串行数据速率的几个关系中的任何一个的参考时钟信号。 该电路在各个方面是可配置的/可重新配置的，其中至少一些配置/重新配置可被动态地控制（即在PLD的用户模式操作期间）。

公开(公告)号：US20070025436A1

公开(公告)日：2007-02-01

申请号：US11192539

申请日：2005-07-28

Applicant: Sergey Shumarayev ,  Wilson Wong ,  Rakesh Patel

Inventor： Sergey Shumarayev ,  Wilson Wong ,  Rakesh Patel

IPC: H03H7/30

CPC classification number: H04L25/03057 ,  H04L2025/0349 ,  H04L2025/03573

Abstract: Equalization circuitry for receiving a digital data signal includes both feed-forward equalizer (“FFE”) circuitry and decision-feedback equalizer (“DFE”) circuitry. The FFE circuitry may be used to give the DFE circuitry a signal that is at least minimally adequate for proper start-up of the DFE circuitry. Thereafter, more of the burden of the equalization task may be shifted from the FFE circuitry to the DFE circuitry.

Abstract translation: 用于接收数字数据信号的均衡电路包括前馈均衡器（“FFE”）电路和判决反馈均衡器（“DFE”）电路。 FFE电路可以用于给DFE电路提供至少最不足以适当启动DFE电路的信号。 此后，均衡任务的更多负担可能从FFE电路转移到DFE电路。