公开(公告)号：US5838038A

公开(公告)日：1998-11-17

申请号：US478620

申请日：1995-06-07

申请人： Daisaburo Takashima ,  Shigeyoshi Watanabe ,  Tohru Ozaki ,  Takeshi Hamamoto ,  Yukihito Oowaki

发明人： Daisaburo Takashima ,  Shigeyoshi Watanabe ,  Tohru Ozaki ,  Takeshi Hamamoto ,  Yukihito Oowaki

IPC分类号： G11C7/18 ,  H01L27/108

CPC分类号： G11C7/18 ,  G11C2211/4013

摘要： A semiconductor memory device includes active regions arranged on a semiconductor substrate such that those of the active regions which are adjacent in the word line direction deviate in the bit line direction, MOS transistors respectively formed in the active regions and each having a source and a drain one of which is connected to the bit line, a plurality of trenches each arranged to another set of source an drain regions and arranged to deviate in the word line direction in the respective active regions, those of the trenches which are adjacent with a through word line disposed therebetween being arranged to deviate in the bit line direction so as to be set closer to each other, a plurality of storage electrodes respectively formed in the trenches with capacitor insulative films disposed therebetween, and connection electrodes arranged between the word lines and each connecting the other of the source and drain to the storage electrode.

摘要翻译： 半导体存储器件包括布置在半导体衬底上的有源区域，使得在字线方向上相邻的有源区域在位线方向偏离的有源区域分别形成在有源区域中并且各自具有源极和漏极 其中一个连接到位线，多个沟槽，每个沟槽被布置成另一组源极漏极区域，并且被布置成在相应的有源区域中的字线方向偏离，与通过字相邻的沟槽的那些沟槽 配置在它们之间的线被布置为在位线方向上偏离以使得彼此更靠近，分别形成在沟槽中的多个存储电极，其中设置有电容器绝缘膜，以及布置在字线和每个连接之间的连接电极 另一个源极和漏极到存储电极。

公开(公告)号：US5455601A

公开(公告)日：1995-10-03

申请号：US202579

申请日：1994-02-28

申请人： Tohru Ozaki

发明人： Tohru Ozaki

IPC分类号： G06F3/00 ,  G06F3/01 ,  G06T1/00 ,  G09G5/00 ,  G09G5/30 ,  G09G5/34 ,  G09G5/399 ,  G09G3/02

CPC分类号： G06F3/013 ,  G09G5/00 ,  G09G5/30 ,  G09G5/399 ,  G09G2320/0261

摘要： A display section displays an image to be displayed on a screen. An image processing section detects an opening/closing of an operator's eyelids on the basis of an image of the operator's face. A display controlling section changes the video data displayed on the display screen through a display section on the basis of the eyelid opening/closing state detected by the image processing section in accordance with a timing at which the operator does not look at the display screen.

摘要翻译： 显示部分显示要在屏幕上显示的图像。 图像处理部根据操作人脸的图像来检测操作者的眼皮的开闭。 显示控制部分根据由图像处理部分检测到的眼睑打开/关闭状态，根据操作者看不到显示屏幕的时间，通过显示部分改变显示屏幕上显示的视频数据。

公开(公告)号：US5331425A

公开(公告)日：1994-07-19

申请号：US818572

申请日：1992-01-09

申请人： Tohru Ozaki ,  Hitoshi Horie ,  Hideyuki Shirai

发明人： Tohru Ozaki ,  Hitoshi Horie ,  Hideyuki Shirai

IPC分类号： G06T9/00 ,  H04N1/413 ,  H04N1/41

CPC分类号： H04N1/413

摘要： A data encoding apparatus, applicable for example to a facsimile apparatus, increases the degree of image data compression that can be achieved by a variable length encoding scheme, by limiting the maximum amount of data outputted from the encoding apparatus for each scan line to the amount of unencoded image data in a scan line. Generation of increased amounts of data in the case of certain types of image content, as a result of the variable length encoding, is thereby eliminated with a consequent increase in encoding efficiency.

摘要翻译： 可应用于传真装置的数据编码装置通过将从每个扫描线的编码装置输出的最大数据量限制为数量，从而增加可变长度编码方案可以实现的图像数据压缩的程度 的扫描线中未编码的图像数据。 因此，由于可变长度编码的结果，在某些类型的图像内容的情况下增加的数据量的产生被消除，从而导致编码效率的提高。

公开(公告)号：US4736315A

公开(公告)日：1988-04-05

申请号：US722559

申请日：1985-04-12

申请人： Tohru Ozaki ,  Takashi Toriu ,  Hiromichi Iwase

发明人： Tohru Ozaki ,  Takashi Toriu ,  Hiromichi Iwase

IPC分类号： G06K9/52 ,  G06T7/40 ,  G03G15/00

CPC分类号： G06T7/401 ,  G06T7/0002 ,  G06T2207/30168

摘要： An apparatus for evaluating density-evenness of patterns printed on an article includes a circuit for calculating density distribution of the image data in each segment; a circuit for normalizing the density distribution with an area of effective image data in each segment; and a circuit for quantifying the density and evenness of the patterns.

摘要翻译： 用于评估印刷在物品上的图案的密度均匀性的装置包括用于计算每个片段中的图像数据的浓度分布的电路; 用于在每个段中用有效图像数据的区域归一化密度分布的电路; 以及用于量化图案的密度和均匀性的电路。

公开(公告)号：US20130049098A1

公开(公告)日：2013-02-28

申请号：US13412999

申请日：2012-03-06

申请人： Tatsuo IZUMI ,  Tohru Ozaki

发明人： Tatsuo IZUMI ,  Tohru Ozaki

IPC分类号： H01L29/792 ,  H01L21/425

CPC分类号： H01L29/7881 ,  H01L21/764 ,  H01L27/11524 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/66825

摘要： In one embodiment, a nonvolatile semiconductor memory device includes a substrate, and a plurality of cell transistors, each of which includes a first insulating layer, a charge storage layer, a second insulating layer, and a control electrode successively provided on the substrate, side surfaces of the charge storage layer including inclined surfaces. The device further includes at least one insulator including a first insulator part provided on side surfaces of the cell transistors and on a top surface of the semiconductor substrate between the cell transistors, and a second insulator part continuously provided on an air gap between the cell transistors and on the cell transistors. A first distance from the top surface of the semiconductor substrate between the cell transistors to a bottom end of the air gap is greater than a thickness of the at least one insulator provided on the side surfaces of the cell transistors.

摘要翻译： 在一个实施例中，非易失性半导体存储器件包括基板和多个单元晶体管，每个单元晶体管包括依次设置在基板上的第一绝缘层，电荷存储层，第二绝缘层和控制电极 电荷存储层的表面包括倾斜表面。 该器件还包括至少一个绝缘体，其包括设置在单元晶体管的侧表面上的第一绝缘体部分和在单元晶体管之间的半导体衬底的顶表面上，以及连续地设置在单元晶体管之间的气隙上的第二绝缘体部 并在单元晶体管上。 从单元晶体管之间的半导体衬底的顶表面到气隙的底端的第一距离大于设置在单元晶体管的侧表面上的至少一个绝缘体的厚度。

公开(公告)号：US08362533B2

公开(公告)日：2013-01-29

申请号：US12869502

申请日：2010-08-26

申请人： Tohru Ozaki

发明人： Tohru Ozaki

IPC分类号： H01L21/02

CPC分类号： H01L28/60 ,  G11C11/22 ,  H01L27/105 ,  H01L27/11502 ,  H01L27/11507 ,  H01L27/11509 ,  H01L28/55

摘要： According to an aspect of the present invention, there is provided a semiconductor device including: a transistor including: a source, a drain and a gate; first and second plugs on the source and the drain; a third plug on the gate to have a top face higher than that of the first plug; an interlayer insulating film covering the transistor and the first to the third plugs; a ferroelectric capacitor on the interlayer insulating film, one electrode thereof being connected to the first plug; a barrier film covering surfaces of the ferroelectric capacitor and the interlayer insulating film to prevent a substance affecting the ferroelectric capacitor from entering therethrough; and fourth and fifth plugs disposed on the second and the third plugs and connected thereto through connection holes formed in the barrier film.

摘要翻译： 根据本发明的一个方面，提供了一种半导体器件，包括：晶体管，包括：源极，漏极和栅极; 源极和漏极上的第一和第二插头; 栅极上的第三个插头具有高于第一插头的顶面; 覆盖晶体管和第一至第三插头的层间绝缘膜; 层间绝缘膜上的铁电电容器，其一个电极连接到第一插头; 覆盖铁电电容器和层间绝缘膜的表面的阻挡膜，以防止影响铁电电容器的物质进入其中; 以及设置在第二和第三插头上的第四和第五插头，并且通过形成在阻挡膜中的连接孔与其连接。

公开(公告)号：US08283791B2

公开(公告)日：2012-10-09

申请号：US13051652

申请日：2011-03-18

申请人： Takayuki Toba ,  Tohru Ozaki ,  Toshiki Hisada ,  Hiromitsu Mashita ,  Takafumi Taguchi

发明人： Takayuki Toba ,  Tohru Ozaki ,  Toshiki Hisada ,  Hiromitsu Mashita ,  Takafumi Taguchi

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76816 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11531 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one embodiment, a semiconductor device includes a plurality of first interconnects, a second interconnect, a third interconnect, and a plurality of conductive members. The plurality of first interconnects are arranged periodically to extend in one direction. The second interconnect is disposed outside a group of the plurality of first interconnects to extend in the one direction. The third interconnect is provided between the group and the second interconnect. The plurality of conductive members are disposed on a side opposite to the group as viewed from the second interconnect. A shortest distance between the first interconnect and the third interconnect, a shortest distance between the third interconnect and the second interconnect, and a shortest distance between the first interconnects are equal. A shortest distance between the second interconnect and the conductive member is longer than the shortest distance between the first interconnects.

摘要翻译： 根据一个实施例，半导体器件包括多个第一互连，第二互连，第三互连和多个导电构件。 多个第一互连周期性地布置成在一个方向上延伸。 第二互连设置在多个第一互连的一组之外，以在一个方向上延伸。 第三互连设置在组和第二互连之间。 多个导电构件设置在从第二互连件观察的与组相反的一侧上。 第一互连和第三互连之间的最短距离，第三互连和第二互连之间的最短距离以及第一互连之间的最短距离相等。 第二互连和导电构件之间的最短距离比第一互连之间的最短距离长。

公开(公告)号：US07821047B2

公开(公告)日：2010-10-26

申请号：US11862721

申请日：2007-09-27

申请人： Tohru Ozaki

发明人： Tohru Ozaki

IPC分类号： H01L27/108

CPC分类号： H01L27/11507 ,  H01L27/105 ,  H01L27/11502 ,  H01L28/40 ,  H01L29/66621 ,  H01L29/78 ,  H01L29/7834

摘要： According to an aspect of the present invention, there is provided a semiconductor apparatus including: a semiconductor substrate; an element isolation region formed in the semiconductor substrate so as to extend in a first direction; a gate electrode formed in the semiconductor substrate so as to extend in a second direction crossing the first direction and to penetrate through the element isolation region; a gate insulating film interposed between the gate electrode and the semiconductor substrate; an interlayer dielectric film formed on the gate electrode; a ferroelectric capacitor including: first and second electrodes disposed on the interlayer dielectric film and a ferroelectric between the first and second electrodes; and first and second semiconductor pillars being in contact respectively with the first and second electrodes.

摘要翻译： 根据本发明的一个方面，提供一种半导体装置，包括：半导体衬底; 形成在所述半导体衬底中以沿第一方向延伸的元件隔离区; 形成在所述半导体衬底中以沿与所述第一方向交叉的第二方向延伸并穿过所述元件隔离区域的栅电极; 插入在所述栅极电极和所述半导体衬底之间的栅极绝缘膜; 形成在栅电极上的层间绝缘膜; 铁电电容器，包括：设置在层间电介质膜上的第一电极和第二电极以及第一和第二电极之间的铁电体; 并且第一和第二半导体柱分别与第一和第二电极接触。

公开(公告)号：US07763920B2

公开(公告)日：2010-07-27

申请号：US11898297

申请日：2007-09-11

申请人： Yoshinori Kumura ,  Tohru Ozaki ,  Iwao Kunishima

发明人： Yoshinori Kumura ,  Tohru Ozaki ,  Iwao Kunishima

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L27/11502 ,  H01L27/11507 ,  H01L28/55

摘要： According to an aspect of the present invention, there is provided a semiconductor memory including a lower electrode, a first insulating region formed in the same layer as the lower electrode, a ferroelectric film formed on the lower electrode and on the first insulating region, an upper electrode formed on the ferroelectric film, a second insulating region formed in the same layer as the upper electrode and a transistor. The first insulating region partitions the lower electrode. The second insulating region partitions the upper electrode. The transistor includes a first impurity region connected to the lower electrode and a second impurity region connected to the upper electrode. At least one of the first insulating region and the second insulating region is formed by insulating the lower electrode or the upper electrode.

摘要翻译： 根据本发明的一个方面，提供了一种半导体存储器，其包括下电极，与下电极形成在同一层中的第一绝缘区域，形成在下电极和第一绝缘区上的强电介质膜， 形成在强电介质膜上的上电极，形成在与上电极相同的层中的第二绝缘区域和晶体管。 第一绝缘区域分隔下电极。 第二绝缘区域分隔上电极。 晶体管包括连接到下电极的第一杂质区和连接到上电极的第二杂质区。 通过使下部电极或上部电极绝缘来形成第一绝缘区域和第二绝缘区域中的至少一个。

公开(公告)号：US20100117128A1

公开(公告)日：2010-05-13

申请号：US12564728

申请日：2009-09-22

申请人： Saku Hashiura ,  Yoshinori Kumura ,  Tohru Ozaki

发明人： Saku Hashiura ,  Yoshinori Kumura ,  Tohru Ozaki

IPC分类号： H01L27/108 ,  H01L21/8242

CPC分类号： H01L27/11507 ,  H01L28/55 ,  H01L28/60 ,  H01L28/65 ,  H01L28/75

摘要： A semiconductor memory device has a semiconductor substrate, an impurity diffusion layer that is formed at a surface portion of the semiconductor substrate, an interlayer insulating film that is formed on the semiconductor substrate, a contact plug that penetrates the interlayer insulating film, has a top surface formed higher than a top surface of the interlayer insulating film, a region having a convex shape formed higher than the top surface of the interlayer insulating film, and contacts the impurity diffusion layer, a lower capacitor electrode film that is formed on the contact plug and a predetermined region of the interlayer insulating film, a ferroelectric film that is formed on the lower capacitor electrode film, and an upper capacitor electrode film that is formed on the ferroelectric film.

摘要翻译： 半导体存储器件具有半导体衬底，形成在半导体衬底的表面部分的杂质扩散层，形成在半导体衬底上的层间绝缘膜，穿透层间绝缘膜的接触插塞具有顶部 表面形成为比层间绝缘膜的顶表面高的区域，具有形成为高于层间绝缘膜的顶表面的凸形的区域，并且与杂质扩散层接触;形成在接触插塞上的下电容器电极膜 层间绝缘膜的预定区域，形成在下部电容器电极膜上的铁电体膜和形成在强电介质膜上的上部电容电极膜。