摘要:
An image processing system mainly used in an image verification system for detecting and correcting distortion of an input image includes the following devices; an image memory for storing a digitized image before, during, and after correction, a working memory for temporarily storing intermediate data of the image on correction, density level extension devices for extending the density level or gradation of the image by repeatedly reading out the contents of the image memory and the working memory by using a matrix window containing picture elements of the image, a density slope detection device for detecting the extended density level and calculating a density slope or gradient by using the matrix window, and a correction device for correcting density distribution and line width of the image based on the extended density level and the calculated density slope.
摘要:
An apparatus for evaluating density-evenness of patterns printed on an article includes a circuit for calculating density distribution of the image data in each segment; a circuit for normalizing the density distribution with an area of effective image data in each segment; and a circuit for quantifying the density and evenness of the patterns.
摘要:
In one embodiment, a nonvolatile semiconductor memory includes a memory cell array, a first silicon nitride film and a second silicon nitride film. The memory cell array includes NAND cell units. Each of the NAND cell units has memory cell transistors, a source-side select gate transistor and a drain-side select gate transistor. The source-side select gate transistors is disposed in such a manner as to face each other and the drain-side select gate transistors is disposed in such a manner as to face each other. The first silicon nitride film is present in a region between the source-side select gate transistors and is disposed at a position lowest from the upper surface of the semiconductor substrate. The second silicon nitride film is formed in a region between the drain-side select gate transistors and is disposed at a position lowest from the upper surface of the semiconductor substrate.
摘要:
According to an aspect of the present invention, there is provided a semiconductor device including: a transistor including: a source, a drain and a gate; first and second plugs on the source and the drain; a third plug on the gate to have a top face higher than that of the first plug; an interlayer insulating film covering the transistor and the first to the third plugs; a ferroelectric capacitor on the interlayer insulating film, one electrode thereof being connected to the first plug; a barrier film covering surfaces of the ferroelectric capacitor and the interlayer insulating film to prevent a substance affecting the ferroelectric capacitor from entering therethrough; and fourth and fifth plugs disposed on the second and the third plugs and connected thereto through connection holes formed in the barrier film.
摘要:
A semiconductor memory device, comprising: a semiconductor substrate; a memory cell section comprising a memory transistor provided on the semiconductor substrate, the memory transistor including a first gate electrode provided on the semiconductor substrate with a gate insulating film interposed therebetween, and a source and drain provided at both sides of the first gate electrode on the semiconductor substrate, and a ferroelectric capacitor provided above the memory transistor, the ferroelectric capacitor including a first electrode film connected to any one of a source and drain of the memory transistor, a second electrode film connected to the other one of the drain and source of the memory transistor, and a ferroelectric film provided between the first electrode film and the second electrode film, the memory cell section having the memory transistor and the ferroelectric capacitor connected in parallel to each other; and a select transistor section, comprising a select transistor provided at an end of the memory cell section, the select transistor including a second gate electrode provided on the semiconductor substrate with the gate insulating film interposed therebetween, and a source and drain provided at both sides of the second gate electrode on the semiconductor substrate, and a third electrode film connected to the source and drain of the select transistor and connected to a bit line via a bit line contact.
摘要:
A memory includes a first interlayer on transistors; a first and second plugs connected to the transistor; ferroelectric capacitors; a second interlayer covering a side surface of the capacitor; a local interconnection connecting the second plug to the upper electrode, wherein two upper electrodes adjacent to each other on the second plug are connected to the second plug, the lower electrodes adjacent to each other on the first plug are connected to the first plug, cell blocks comprising the connected capacitors are arranged, cell blocks adjacent to each other are arranged to be shifted by a half pitch of the local interconnection, a first gap between two capacitors adjacent to each other on the second plug is larger than twice a thickness of the second interlayer, and a second gap between the cell blocks adjacent to each other is smaller than twice the thickness of the second interlayer.
摘要:
This disclosure concerns a memory including transistors provided on a substrate; ferroelectric capacitors provided on the transistors, the ferroelectric capacitors respectively including a ferroelectric film provided between a lower electrode and an upper electrode; and a barrier film covering a first side surface of the ferroelectric capacitor, and blocking passing of hydrogen, wherein adjacent two of the ferroelectric capacitors connected in the lower electrode form one capacitor unit, a plurality of the capacitor units connected in the upper electrode form one capacitor chain, the capacitor units are arranged with a deviation of a half pitch of the capacitor unit in adjacent plurality of capacitor chains, and when D1 is a distance between the adjacent ferroelectric capacitors within the capacitor unit, D2 is a distance between the adjacent capacitor chains, and D3 is a distance between the adjacent capacitor units within the capacitor chain, D3 is larger than D1 and D2.
摘要:
There is provided a semiconductor storage device comprising a ferroelectric capacitor superior in barrier capability against penetration of hydrogen from all directions including a transverse direction. The device comprises a transistor formed on a semiconductor substrate, the ferroelectric capacitor formed above the transistor and including a lower electrode, a ferroelectric film, and an upper electrode, a first hydrogen barrier film which continuously surrounds side portions of a ferroelectric capacitor cell array constituted of a plurality of ferroelectric capacitors, and a second hydrogen barrier film which is formed above the ferroelectric capacitor cell array and which is brought into contact with the first hydrogen barrier film in the whole periphery.
摘要:
A semiconductor memory device includes a row of memory cells connected in series, each of the memory cells including a ferroelectric capacitor and a cell transistor having a gate terminal and source/drain terminals, the source/drain terminals being connected in parallel with two electrodes of the ferroelectric capacitor, a word line connected to the gate terminal, memory cell blocks each including the row of memory cells and a block select transistor, a drain terminal of the block select transistor being connected to one end of the row of memory cells, a plate line connected to another end thereof, a bit line connected to a source terminal of the block select transistor, and a block select line connected to a gate terminal of the block select transistor, wherein a contact is provided under the plate line to connect the source terminal of the block select transistor and the bit line.
摘要:
A transistor including a source/drain region is formed on a semiconductor substrate. A plug electrode is formed on the source/drain region. A conductive film is formed on the plug electrode. A first insulation film is formed on the conductive film. A lower electrode is formed on the first insulation film, and electrically connected to the conductive film formed on the plug electrode. A ferroelectric film is formed on the lower electrode. An upper electrode is formed on the ferroelectric film.