公开(公告)号：US10204996B2

公开(公告)日：2019-02-12

申请号：US15668708

申请日：2017-08-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Ching-Chung Yang ,  Wen-Fang Lee ,  Nien-Chung Li ,  Chih-Chung Wang

IPC: H01L29/423 ,  G06F17/50 ,  H01L23/535 ,  H01L29/06 ,  H01L29/78 ,  H01L29/49 ,  H01L29/08 ,  H01L29/66

Abstract: A method of forming a gate layout includes providing a gate layout design diagram comprising at least one gate pattern, disposing at least one insulating plug pattern in the gate pattern for producing a modified gate layout in a case where any one of a length and a width of the gate pattern is greater than or equal to a predetermined size, and outputting and manufacturing the modified gate layout onto a photomask. The predetermined size is determined by a process ability limit, and the process ability limit is a smallest gate size causing gate dishing when a chemical mechanical polishing process is performed to a gate.

公开(公告)号：US20180233416A1

公开(公告)日：2018-08-16

申请号：US15953537

申请日：2018-04-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Kuan-Liang Liu

IPC: H01L21/8234 ,  H01L21/311 ,  H01L27/088 ,  H01L29/49 ,  H01L21/3105 ,  H01L21/02 ,  H01L29/40

CPC classification number: H01L21/823481 ,  H01L21/0217 ,  H01L21/31053 ,  H01L21/31105 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/401 ,  H01L29/4966

Abstract: A method for manufacturing a semiconductor device and a device manufactured using the same are provided. According to a method approach of the embodiment, a substrate having at least a first area with a plurality of polysilicon gates and a second area adjacent to the first area is provided. A contact etch stop layer (CESL) over the polysilicon gates of the first area is formed, and the CESL extends to the second area. Then, a dielectric layer is formed on the CESL, and a nitride layer is formed on the dielectric layer. The nitride layer is patterned to expose the dielectric layer in the first area and to form a pattern of dummy nitrides on the dielectric layer in the second area.

公开(公告)号：US10008573B1

公开(公告)日：2018-06-26

申请号：US15450030

申请日：2017-03-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Hsuan-Kai Chen ,  Tun-Jen Cheng

IPC: H01L29/66 ,  H01L29/40 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L29/404 ,  H01L29/0653 ,  H01L29/402 ,  H01L29/42364 ,  H01L29/4238 ,  H01L29/7833 ,  H01L29/7835

Abstract: A high-voltage metal-oxide-semiconductor transistor device includes a semiconductor substrate, a gate structure, a first drift region, a first isolation structure, a drain region, and a first sub-gate structure. The gate structure and the first sub-gate structure are disposed on the semiconductor substrate and separated from each other. The first drift region is disposed in the semiconductor substrate and disposed at one side of the gate structure. The first isolation structure and the drain region are disposed in the first drift region and separated from each other. A part of the first drift region is disposed between the drain region and the first isolation structure. The first sub-gate structure is at least partially disposed on the first drift region disposed between the drain region and the first isolation structure, and the first sub-gate structure is electrically connected to the drain region.

公开(公告)号：US09985129B2

公开(公告)日：2018-05-29

申请号：US15820467

申请日：2017-11-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Kuan-Liang Liu ,  Ching-Chung Yang ,  Kai-Kuen Chang ,  Ping-Hung Chiang ,  Nien-Chung Li ,  Wen-Fang Lee ,  Chih-Chung Wang

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L21/033

CPC classification number: H01L29/7823 ,  H01L21/033 ,  H01L29/0619 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/4238 ,  H01L29/66545 ,  H01L29/66681

Abstract: A high-voltage MOS transistor includes a semiconductor substrate, a gate oxide layer on the semiconductor substrate, a gate on the gate oxide layer, a spacer covering a sidewall of the gate, a source on one side of the gate, and a drain on the other side of the gate. The gate includes at least a first discrete segment and a second discrete segment. The first discrete segment is not in direct contact with the second discrete segment. The spacer fills into a gap between the first discrete segment and the second discrete segment.

公开(公告)号：US20180005835A1

公开(公告)日：2018-01-04

申请号：US15705014

申请日：2017-09-14

Applicant: United Microelectronics Corp.

Inventor： Kun-Huang Yu ,  Shih-Yin Hsiao

IPC: H01L21/28 ,  H01L27/11536 ,  H01L27/11539 ,  H01L29/423

CPC classification number: H01L29/40114 ,  H01L27/11536 ,  H01L27/11539 ,  H01L29/42336

Abstract: Provided is a memory device including a first gate, a second gate and an inter-gate dielectric layer. The first gate is buried in a substrate. The second gate includes metal and is disposed on the substrate. The inter-gate dielectric layer is disposed between the first and second gates. The inter-gate dielectric layer comprises a high-k layer having a dielectric constant of greater than about 10.

公开(公告)号：US09859417B2

公开(公告)日：2018-01-02

申请号：US15191535

申请日：2016-06-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Kuan-Liang Liu ,  Ching-Chung Yang ,  Kai-Kuen Chang ,  Ping-Hung Chiang ,  Nien-Chung Li ,  Wen-Fang Lee ,  Chih-Chung Wang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/10

CPC classification number: H01L29/7823 ,  H01L21/033 ,  H01L29/0619 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/4238 ,  H01L29/66545 ,  H01L29/66681

Abstract: A high-voltage MOS transistor includes a semiconductor substrate, a gate oxide layer on the semiconductor substrate, a gate on the gate oxide layer, a spacer covering a sidewall of the gate, a source on one side of the gate, and a drain on the other side of the gate. The gate includes at least a first discrete segment and a second discrete segment. The first discrete segment is not in direct contact with the second discrete segment. The spacer fills into a gap between the first discrete segment and the second discrete segment.

公开(公告)号：US20170345926A1

公开(公告)日：2017-11-30

申请号：US15191535

申请日：2016-06-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Kuan-Liang Liu ,  Ching-Chung Yang ,  Kai-Kuen Chang ,  Ping-Hung Chiang ,  Nien-Chung Li ,  Wen-Fang Lee ,  Chih-Chung Wang

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/10 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/7823 ,  H01L21/033 ,  H01L29/0619 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/4238 ,  H01L29/66545 ,  H01L29/66681

Abstract: A high-voltage MOS transistor includes a semiconductor substrate, a gate oxide layer on the semiconductor substrate, a gate on the gate oxide layer, a spacer covering a sidewall of the gate, a source on one side of the gate, and a drain on the other side of the gate. The gate includes at least a first discrete segment and a second discrete segment. The first discrete segment is not in direct contact with the second discrete segment. The spacer fills into a gap between the first discrete segment and the second discrete segment.

公开(公告)号：US09761657B2

公开(公告)日：2017-09-12

申请号：US14952877

申请日：2015-11-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Ching-Chung Yang ,  Wen-Fang Lee ,  Nien-Chung Li ,  Chih-Chung Wang

IPC: H01L29/06 ,  H01L29/78 ,  G06F17/50 ,  H01L23/535

CPC classification number: H01L29/4238 ,  G06F17/5072 ,  H01L23/535 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7835 ,  H01L29/7836 ,  H01L29/785

Abstract: A metal-oxide-semiconductor transistor includes a substrate, a gate insulating layer disposed on the surface of the substrate layer, a metal gate disposed on the gate insulating layer and having at least one plug hole, at least one dielectric plug disposed in the plug hole, and two diffusion regions disposed at two sides of the metal gate in the substrate. The metal gate is configured to operate under an operation voltage greater than 5 v.

公开(公告)号：US09728616B2

公开(公告)日：2017-08-08

申请号：US14922209

申请日：2015-10-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Kai-Kuen Chang

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/4232 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7835

Abstract: The present invention provides a high-voltage metal-oxide-semiconductor transistor device and a manufacturing method thereof. First, a semiconductor substrate is provided and a dielectric layer and a conductive layer sequentially stacked on the semiconductor substrate. Then, the conductive layer is patterned to form a gate and a dummy gate disposed at a first side of the gate and followed by forming a first spacer between the gate and the dummy gate and a second spacer at a second side of the gate opposite to the first side, wherein the first spacer includes an indentation. Subsequently, the dummy gate is removed.

公开(公告)号：US09653558B2

公开(公告)日：2017-05-16

申请号：US14739702

申请日：2015-06-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Kai-Kuen Chang ,  Kun-Huang Yu

IPC: H01L27/088 ,  H01L29/40 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/10

CPC classification number: H01L29/404 ,  H01L21/762 ,  H01L23/485 ,  H01L23/522 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a source region, a drain region, a gate, and a dummy contact. The source region and the drain region are formed in the substrate. The gate is formed on the substrate and between the source region and the drain region. The dummy contact includes a plurality of dummy plugs formed on the substrate, wherein the dummy plugs have depths decreasing towards the drain region.